📄 videogenerator.twr
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Lattice TRACE Report, Version ispLever_v61_PROD_Build (37)
Sat Jun 16 17:36:33 2007
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2006 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -o checkpnt.twr videogenerator.ncd videogenerator.prf
Design file: videogenerator.ncd
Preference file: videogenerator.prf
Device,speed: LFXP3C,3
Report level: verbose report, limited to 1 item per preference
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BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "clk" 86.866000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 9.593ns
The internal maximum frequency of the following component is 521.376 MHz
Logical Details: Cell type Pin type Component name
Source: FSLICE Clock SLICE_14
Destination: FSLICE Data in SLICE_14
Delay: 1.918ns -- based on Minimum Pulse Width
Report: 521.376MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "clk_c" 86.866000 MHz ;
4096 items scored, 4096 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 4.492ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q countforvertical_6 (from clk_c -)
Destination: FF Data in VGAdenaZ0 (to clk_c -)
Delay: 15.824ns (38.3% logic, 61.7% route), 12 logic levels.
Constraint Details:
15.824ns physical path delay SLICE_37 to SLICE_14 exceeds
11.511ns delay constraint less
0.000ns skew and
0.179ns DIN_SET requirement (totaling 11.332ns) by 4.492ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.631 R18C8D.CLK to R18C8D.Q1 SLICE_37 (from clk_c)
ROUTE 3 2.067 R18C8D.Q1 to R17C5D.A0 countforverticalZ0Z_6
A0TOFCO_DE --- 0.907 R17C5D.A0 to R17C5D.FCO SLICE_4
ROUTE 1 0.000 R17C5D.FCO to R17C6A.FCI un1_countforvertical_0_cry_7
FCITOFCO_D --- 0.145 R17C6A.FCI to R17C6A.FCO SLICE_3
ROUTE 1 0.000 R17C6A.FCO to R17C6B.FCI un1_countforvertical_0_cry_9
TLATCH_DEL --- 1.324 R17C6B.FCI to R17C6B.Q1 SLICE_2
ROUTE 5 1.517 R17C6B.Q1 to R16C5D.C1 un1_countforvertical_n_11
CTOF_DEL --- 0.382 R16C5D.C1 to R16C5D.F1 SLICE_72
ROUTE 1 0.653 R16C5D.F1 to R16C6A.A0 g0_13_L10_LZ0Z8
CTOF_DEL --- 0.382 R16C6A.A0 to R16C6A.F0 SLICE_69
ROUTE 1 1.081 R16C6A.F0 to R16C8B.D0 g0_13_LZ0Z10
CTOF_DEL --- 0.382 R16C8B.D0 to R16C8B.F0 SLICE_68
ROUTE 1 0.913 R16C8B.F0 to R17C8B.C1 g0_13Z0Z_1
CTOF_DEL --- 0.382 R17C8B.C1 to R17C8B.F1 SLICE_61
ROUTE 7 0.983 R17C8B.F1 to R17C7C.C0 countforvertical_3_sn_N_2
CTOF_DEL --- 0.382 R17C7C.C0 to R17C7C.F0 SLICE_46
ROUTE 1 1.123 R17C7C.F0 to R18C7B.B0 g0_iZ0Z_0
CTOF_DEL --- 0.382 R18C7B.B0 to R18C7B.F0 SLICE_75
ROUTE 1 0.511 R18C7B.F0 to R18C7A.C0 un69_pixelclocklto6_d
CTOF_DEL --- 0.382 R18C7A.C0 to R18C7A.F0 SLICE_44
ROUTE 1 0.913 R18C7A.F0 to R18C8A.C0 un65_pixelclock_5Z0Z_1
CTOF_DEL --- 0.382 R18C8A.C0 to R18C8A.F0 SLICE_14
ROUTE 1 0.000 R18C8A.F0 to R18C8A.DI0 VGAdena_0_sqmuxa_1 (to clk_c)
--------
15.824 (38.3% logic, 61.7% route), 12 logic levels.
Clock Skew Details:
Source Clock:
Delay Connection
4.679ns 20.PADDI to R18C8D.CLK
Destination Clock:
Delay Connection
4.679ns 20.PADDI to R18C8A.CLK
Warning: 62.488MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "clk" 86.866000 MHz ; | 86.866 MHz| 521.376 MHz| 0
| | |
FREQUENCY NET "clk_c" 86.866000 MHz ; | 86.866 MHz| 62.488 MHz| 12
| | |
----------------------------------------------------------------------------
1 preference not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
VGAdena_0_sqmuxa_1 | 1| 4096| 100.00%
| | |
un65_pixelclock_5Z0Z_1 | 1| 3694| 90.19%
| | |
un25_pixelclockZ0 | 15| 2341| 57.15%
| | |
un2_countforhorizontal_1_0_cry_5 | 1| 1884| 46.00%
| | |
un25_pixelclockZ0Z_1 | 1| 1675| 40.89%
| | |
un2_countforhorizontal_1_0_cry_7 | 1| 1656| 40.43%
| | |
un2_countforhorizontal_1_0_cry_3 | 1| 1598| 39.01%
| | |
countforvertical_3_sn_N_2 | 7| 1486| 36.28%
| | |
un69_pixelclocklto6_d | 1| 1459| 35.62%
| | |
un65_pixelclock_5_1Z0Z_1 | 1| 1190| 29.05%
| | |
g0_13Z0Z_1 | 1| 1150| 28.08%
| | |
un2_countforhorizontal_1_0_cry_9 | 1| 1120| 27.34%
| | |
un2_countforhorizontal_1_0_cry_1 | 1| 1062| 25.93%
| | |
VGAdena_0_sqmuxa_1_0_m2_i_a3_1 | 1| 990| 24.17%
| | |
un25_pixelclock_7_m2_0_a2_a0_xZ0 | 1| 882| 21.53%
| | |
un25_pixelclock_0 | 2| 661| 16.14%
| | |
N_182_2 | 13| 628| 15.33%
| | |
countforhorizontal_fastZ0Z_0 | 2| 612| 14.94%
| | |
countforvertical_3Z0Z_8 | 3| 612| 14.94%
| | |
g0_13_LZ0Z10 | 1| 587| 14.33%
| | |
un25_pixelclock_7_m2_0_a2_a0_x_sx | 2| 564| 13.77%
| | |
un2_countforhorizontal_1_n_11 | 5| 562| 13.72%
| | |
un25_pixelclock_L1_sxZ0 | 1| 557| 13.60%
| | |
countforvertical_3_2 | 3| 535| 13.06%
| | |
countforhorizontalZ0Z_1 | 1| 522| 12.74%
| | |
N_176_1 | 3| 488| 11.91%
| | |
countforvertical_3_3 | 3| 480| 11.72%
| | |
un2_countforhorizontal_1_0_cry_11 | 1| 474| 11.57%
| | |
un2_countforhorizontal_1_n_12 | 6| 474| 11.57%
| | |
countforhorizontalZ0Z_2 | 1| 471| 11.50%
| | |
g0_iZ0Z_0 | 1| 462| 11.28%
| | |
un69_pixelclocklto6_0 | 2| 427| 10.42%
| | |
countforvertical_3_sn_m1_0_LZ0Z1 | 1| 419| 10.23%
| | |
un65_pixelclock_dZ0Z_0 | 1| 417| 10.18%
| | |
un2_countforhorizontal_1_n_9 | 8| 415| 10.13%
| | |
countforhorizontalZ0Z_4 | 1| 414| 10.11%
| | |
un2_countforhorizontal_1_n_7 | 5| 413| 10.08%
| | |
----------------------------------------------------------------------------
Timing summary:
---------------
Timing errors: 4096 Score: 10515157
Cumulative negative slack: 10515157
Constraints cover 19091 paths, 1 nets, and 569 connections (98.4% coverage)
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