videogenerator.vhm

用lattice XP3 demo板设计的VGA信号发生器

  II_G_76: AND2 port map (
      O => N_618,
      I0 => COUNTFORVERTICAL(1),
      I1 => COUNTFORVERTICAL_3(0));
  \II_countforvertical_0_4_.r\: INV port map (
      O => \COUNTFORVERTICAL_0_4_.UN3\,
      I0 => PIXELCLOCK);
  \II_countforvertical_0_4_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_0_4_.UN1\,
      I0 => COUNTFORVERTICAL_3(4),
      I1 => PIXELCLOCK);
  \II_countforvertical_0_4_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_0_4_.UN0\,
      I0 => COUNTFORVERTICAL(4),
      I1 => \COUNTFORVERTICAL_0_4_.UN3\);
  \II_countforvertical_0_4_.p\: OR2 port map (
      O => N_7,
      I0 => \COUNTFORVERTICAL_0_4_.UN1\,
      I1 => \COUNTFORVERTICAL_0_4_.UN0\);
  II_countforvertical_3_sn_m1: AND2 port map (
      O => COUNTFORVERTICAL_3_SN_N_2,
      I0 => UN25_PIXELCLOCK,
      I1 => UN29_PIXELCLOCK);
  \II_countforvertical_3_8_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_8_.UN3\,
      I0 => COUNTFORVERTICAL_3_SN_N_2);
  \II_countforvertical_3_8_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_8_.UN1\,
      I0 => UN25_PIXELCLOCK_I_0,
      I1 => COUNTFORVERTICAL_3_SN_N_2);
  \II_countforvertical_3_8_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_8_.UN0\,
      I0 => N_255,
      I1 => \COUNTFORVERTICAL_3_8_.UN3\);
  \II_countforvertical_3_8_.p\: OR2 port map (
      O => COUNTFORVERTICAL_3(8),
      I0 => \COUNTFORVERTICAL_3_8_.UN1\,
      I1 => \COUNTFORVERTICAL_3_8_.UN0\);
  \II_countforvertical_3_6_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_6_.UN3\,
      I0 => COUNTFORVERTICAL_3_SN_N_2);
  \II_countforvertical_3_6_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_6_.UN1\,
      I0 => UN25_PIXELCLOCK_I_0,
      I1 => COUNTFORVERTICAL_3_SN_N_2);
  \II_countforvertical_3_6_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_6_.UN0\,
      I0 => N_253,
      I1 => \COUNTFORVERTICAL_3_6_.UN3\);
  \II_countforvertical_3_6_.p\: OR2 port map (
      O => COUNTFORVERTICAL_3(6),
      I0 => \COUNTFORVERTICAL_3_6_.UN1\,
      I1 => \COUNTFORVERTICAL_3_6_.UN0\);
  \II_countforvertical_3_5_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_5_.UN3\,
      I0 => COUNTFORVERTICAL_3_SN_N_2);
  \II_countforvertical_3_5_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_5_.UN1\,
      I0 => UN25_PIXELCLOCK_I_0,
      I1 => COUNTFORVERTICAL_3_SN_N_2);
  \II_countforvertical_3_5_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_5_.UN0\,
      I0 => N_252,
      I1 => \COUNTFORVERTICAL_3_5_.UN3\);
  \II_countforvertical_3_5_.p\: OR2 port map (
      O => COUNTFORVERTICAL_3(5),
      I0 => \COUNTFORVERTICAL_3_5_.UN1\,
      I1 => \COUNTFORVERTICAL_3_5_.UN0\);
  \II_countforvertical_3_3_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_3_.UN3\,
      I0 => COUNTFORVERTICAL_3_SN_N_2);
  \II_countforvertical_3_3_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_3_.UN1\,
      I0 => UN25_PIXELCLOCK_I_0,
      I1 => COUNTFORVERTICAL_3_SN_N_2);
  \II_countforvertical_3_3_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_3_.UN0\,
      I0 => N_250,
      I1 => \COUNTFORVERTICAL_3_3_.UN3\);
  \II_countforvertical_3_3_.p\: OR2 port map (
      O => COUNTFORVERTICAL_3(3),
      I0 => \COUNTFORVERTICAL_3_3_.UN1\,
      I1 => \COUNTFORVERTICAL_3_3_.UN0\);
  II_un25_pixelclock_i: INV port map (
      O => UN25_PIXELCLOCK_I_0,
      I0 => UN25_PIXELCLOCK);
  \II_countforvertical_3_2_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_2_.UN3\,
      I0 => COUNTFORVERTICAL_3_SN_N_2);
  \II_countforvertical_3_2_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_2_.UN1\,
      I0 => UN25_PIXELCLOCK_I_0,
      I1 => COUNTFORVERTICAL_3_SN_N_2);
  \II_countforvertical_3_2_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_2_.UN0\,
      I0 => N_249,
      I1 => \COUNTFORVERTICAL_3_2_.UN3\);
  \II_countforvertical_3_2_.p\: OR2 port map (
      O => COUNTFORVERTICAL_3(2),
      I0 => \COUNTFORVERTICAL_3_2_.UN1\,
      I1 => \COUNTFORVERTICAL_3_2_.UN0\);
  \II_un1_countforvertical_i[1]\: INV port map (
      O => UN1_COUNTFORVERTICAL_I_0(1),
      I0 => UN1_COUNTFORVERTICAL(1));
  \II_countforvertical_i[2]\: INV port map (
      O => COUNTFORVERTICAL_I_0(2),
      I0 => COUNTFORVERTICAL(2));
  \II_countforvertical_3_0_12_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_0_12_.UN3\,
      I0 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_12_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_12_.UN1\,
      I0 => UN1_COUNTFORVERTICAL(12),
      I1 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_12_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_12_.UN0\,
      I0 => COUNTFORVERTICAL(12),
      I1 => \COUNTFORVERTICAL_3_0_12_.UN3\);
  \II_countforvertical_3_0_12_.p\: OR2 port map (
      O => COUNTFORVERTICAL_3(12),
      I0 => \COUNTFORVERTICAL_3_0_12_.UN1\,
      I1 => \COUNTFORVERTICAL_3_0_12_.UN0\);
  \II_countforvertical_3_0_7_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_0_7_.UN3\,
      I0 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_7_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_7_.UN1\,
      I0 => UN1_COUNTFORVERTICAL(7),
      I1 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_7_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_7_.UN0\,
      I0 => COUNTFORVERTICAL(7),
      I1 => \COUNTFORVERTICAL_3_0_7_.UN3\);
  \II_countforvertical_3_0_7_.p\: OR2 port map (
      O => COUNTFORVERTICAL_3(7),
      I0 => \COUNTFORVERTICAL_3_0_7_.UN1\,
      I1 => \COUNTFORVERTICAL_3_0_7_.UN0\);
  II_G_397: XOR2 port map (
      O => UN1_COUNTFORVERTICAL(12),
      I0 => N_489,
      I1 => COUNTFORVERTICAL(12));
  II_G_396: AND2 port map (
      O => N_489,
      I0 => N_486,
      I1 => COUNTFORVERTICAL(11));
  II_G_388: AND2 port map (
      O => N_477,
      I0 => N_474,
      I1 => COUNTFORVERTICAL(7));
  II_G_387: XOR2 port map (
      O => UN1_COUNTFORVERTICAL(7),
      I0 => N_474,
      I1 => COUNTFORVERTICAL(7));
  \II_countforvertical_i[0]\: INV port map (
      O => COUNTFORVERTICAL_I_0(0),
      I0 => COUNTFORVERTICAL(0));
  II_G_271: AND2 port map (
      O => N_348,
      I0 => COUNTFORVERTICAL(1),
      I1 => COUNTFORVERTICAL_I_0(0));
  II_N_249_i: INV port map (
      O => N_249_I_0,
      I0 => N_249);
  II_G_77: AND2 port map (
      O => N_129_1,
      I0 => N_125,
      I1 => N_249_I_0);
  \II_countforvertical_3_i[3]\: INV port map (
      O => COUNTFORVERTICAL_3_I_0(3),
      I0 => COUNTFORVERTICAL_3(3));
  II_G_80: AND2 port map (
      O => N_622,
      I0 => N_129_1_I,
      I1 => COUNTFORVERTICAL_3(3));
  \II_countforvertical_3_i[6]\: INV port map (
      O => COUNTFORVERTICAL_3_I_0(6),
      I0 => COUNTFORVERTICAL_3(6));
  \II_countforvertical_0_2_.r\: INV port map (
      O => \COUNTFORVERTICAL_0_2_.UN3\,
      I0 => PIXELCLOCK);
  \II_countforvertical_0_2_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_0_2_.UN1\,
      I0 => COUNTFORVERTICAL_3(2),
      I1 => PIXELCLOCK);
  \II_countforvertical_0_2_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_0_2_.UN0\,
      I0 => COUNTFORVERTICAL(2),
      I1 => \COUNTFORVERTICAL_0_2_.UN3\);
  \II_countforvertical_0_2_.p\: OR2 port map (
      O => N_5,
      I0 => \COUNTFORVERTICAL_0_2_.UN1\,
      I1 => \COUNTFORVERTICAL_0_2_.UN0\);
  \II_countforvertical_0_3_.r\: INV port map (
      O => \COUNTFORVERTICAL_0_3_.UN3\,
      I0 => PIXELCLOCK);
  \II_countforvertical_0_3_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_0_3_.UN1\,
      I0 => COUNTFORVERTICAL_3(3),
      I1 => PIXELCLOCK);
  \II_countforvertical_0_3_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_0_3_.UN0\,
      I0 => COUNTFORVERTICAL(3),
      I1 => \COUNTFORVERTICAL_0_3_.UN3\);
  \II_countforvertical_0_3_.p\: OR2 port map (
      O => N_6,
      I0 => \COUNTFORVERTICAL_0_3_.UN1\,
      I1 => \COUNTFORVERTICAL_0_3_.UN0\);
  \II_countforvertical_0_5_.r\: INV port map (
      O => \COUNTFORVERTICAL_0_5_.UN3\,
      I0 => PIXELCLOCK);
  \II_countforvertical_0_5_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_0_5_.UN1\,
      I0 => COUNTFORVERTICAL_3(5),
      I1 => PIXELCLOCK);
  \II_countforvertical_0_5_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_0_5_.UN0\,
      I0 => COUNTFORVERTICAL(5),
      I1 => \COUNTFORVERTICAL_0_5_.UN3\);
  \II_countforvertical_0_5_.p\: OR2 port map (
      O => N_8,
      I0 => \COUNTFORVERTICAL_0_5_.UN1\,
      I1 => \COUNTFORVERTICAL_0_5_.UN0\);
  \II_countforvertical_0_6_.r\: INV port map (
      O => \COUNTFORVERTICAL_0_6_.UN3\,
      I0 => PIXELCLOCK);
  \II_countforvertical_0_6_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_0_6_.UN1\,
      I0 => COUNTFORVERTICAL_3(6),
      I1 => PIXELCLOCK);
  \II_countforvertical_0_6_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_0_6_.UN0\,
      I0 => COUNTFORVERTICAL(6),
      I1 => \COUNTFORVERTICAL_0_6_.UN3\);
  \II_countforvertical_0_6_.p\: OR2 port map (
      O => N_9,
      I0 => \COUNTFORVERTICAL_0_6_.UN1\,
      I1 => \COUNTFORVERTICAL_0_6_.UN0\);
  II_G_375: XOR2 port map (
      O => UN1_COUNTFORVERTICAL(1),
      I0 => COUNTFORVERTICAL(0),
      I1 => COUNTFORVERTICAL(1));
  II_G_376: AND2 port map (
      O => N_459,
      I0 => COUNTFORVERTICAL(0),
      I1 => COUNTFORVERTICAL(1));
  II_G_377: XOR2 port map (
      O => UN1_COUNTFORVERTICAL(2),
      I0 => N_459,
      I1 => COUNTFORVERTICAL(2));
  II_G_378: AND2 port map (
      O => N_462,
      I0 => N_459,
      I1 => COUNTFORVERTICAL(2));
  \II_countforvertical_3_0[0]\: XOR2 port map (
      O => COUNTFORVERTICAL_3(0),
      I0 => COUNTFORVERTICAL(0),
      I1 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_1_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_0_1_.UN3\,
      I0 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_1_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_1_.UN1\,
      I0 => UN1_COUNTFORVERTICAL(1),
      I1 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_1_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_1_.UN0\,
      I0 => COUNTFORVERTICAL(1),
      I1 => \COUNTFORVERTICAL_3_0_1_.UN3\);
  \II_countforvertical_3_0_1_.p\: OR2 port map (
      O => COUNTFORVERTICAL_3(1),
      I0 => \COUNTFORVERTICAL_3_0_1_.UN1\,
      I1 => \COUNTFORVERTICAL_3_0_1_.UN0\);
  \II_countforvertical_3_0_9_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_0_9_.UN3\,
      I0 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_9_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_9_.UN1\,
      I0 => UN1_COUNTFORVERTICAL(9),
      I1 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_9_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_9_.UN0\,
      I0 => COUNTFORVERTICAL(9),
      I1 => \COUNTFORVERTICAL_3_0_9_.UN3\);
  \II_countforvertical_3_0_9_.p\: OR2 port map (
      O => COUNTFORVERTICAL_3(9),
      I0 => \COUNTFORVERTICAL_3_0_9_.UN1\,
      I1 => \COUNTFORVERTICAL_3_0_9_.UN0\);
  \II_un1_countforvertical_i[12]\: INV port map (
      O => UN1_COUNTFORVERTICAL_I_0(12),
      I0 => UN1_COUNTFORVERTICAL(12));
  \II_un1_countforvertical_i[9]\: INV port map (
      O => UN1_COUNTFORVERTICAL_I_0(9),
      I0 => UN1_COUNTFORVERTICAL(9));
  \II_un1_countforvertical_i[7]\: INV port map (
      O => UN1_COUNTFORVERTICAL_I_0(7),
      I0 => UN1_COUNTFORVERTICAL(7));
  \II_un1_countforvertical_i[4]\: INV port map (
      O => UN1_COUNTFORVERTICAL_I_0(4),
      I0 => UN1_COUNTFORVERTICAL(4));
  \II_countforhorizontal_0_11_.r\: INV port map (
      O => \COUNTFORHORIZONTAL_0_11_.UN3\,
      I0 => PIXELCLOCK);
  \II_countforhorizontal_0_11_.m\: AND2 port map (
      O => \COUNTFORHORIZONTAL_0_11_.UN1\,
      I0 => UN2_COUNTFORHORIZONTAL_1(11),
      I1 => PIXELCLOCK);
  \II_countforhorizontal_0_11_.n\: AND2 port map (
      O => \COUNTFORHORIZONTAL_0_11_.UN0\,
      I0 => COUNTFORHORIZONTAL(11),
      I1 => \COUNTFORHORIZONTAL_0_11_.UN3\);
  \II_countforhorizontal_0_11_.p\: OR2 port map (
      O => N_34,
      I0 => \COUNTFORHORIZONTAL_0_11_.UN1\,
      I1 => \COUNTFORHORIZONTAL_0_11_.UN0\);
  \II_VGAh_cs_0.r\: INV port map (
      O => \VGAH_CS_0.UN3\,
      I0 => PIXELCLOCK);
  \II_VGAh_cs_0.m\: AND2 port map (
      O => \VGAH_CS_0.UN1\,
      I0 => VGAH_CS_3_IV_I_0,
      I1 => PIXELCLOCK);
  \II_VGAh_cs_0.n\: AND2 port map (
      O => \VGAH_CS_0.UN0\,
      I0 => VGAH_CS_C,
      I1 => \VGAH_CS_0.UN3\);
  \II_VGAh_cs_0.p\: OR2 port map (
      O => N_16,
      I0 => \VGAH_CS_0.UN1\,
      I1 => \VGAH_CS_0.UN0\);
  \II_VGAv_0.r\: INV port map (
      O => \VGAV_0.UN3\,
      I0 => PIXELCLOCK);
  \II_VGAv_0.m\: AND2 port map (
      O => \VGAV_0.UN1\,
      I0 => VGAV_2,
      I1 => PIXELCLOCK);
  \II_VGAv_0.n\: AND2 port map (
      O => \VGAV_0.UN0\,
      I0 => VGAV_C,
      I1 => \VGAV_0.UN3\);
  \II_VGAv_0.p\: OR2 port map (
      O => N_2,
      I0 => \VGAV_0.UN1\,
      I1 => \VGAV_0.UN0\);
  \II_VGAdena_0.r\: INV port map (
      O => \VGADENA_0.UN3\,
      I0 => VGADENA_0_SQMUXA);
  \II_VGAdena_0.m\: AND2 port map (
      O => \VGADENA_0.UN1\,
      I0 => COUNTFORVERTICAL_3(9),
      I1 => VGADENA_0_SQMUXA);
  \II_VGAdena_0.n\: AND2 port map (
      O => \VGADENA_0.UN0\,
      I0 => VGADENA_C,
      I1 => \VGADENA_0.UN3\);
  \II_VGAdena_0.p\: OR2 port map (
      O => N_1,
      I0 => \VGADENA_0.UN1\,
      I1 => \VGADENA_0.UN0\);
  II_G_345: AND2 port map (
      O => N_431,
      I0 => N_428,
      I1 => COUNTFORHORIZONTAL(5));
  II_G_344: XOR2 port map (
      O => N_289,
      I0 => N_428,
      I1 => COUNTFORHORIZONTAL(5));
  II_G_337: AND2 port map (
      O => N_419,
      I0 => COUNTFORHORIZONTAL(0),
      I1 => COUNTFORHORIZONTAL(1));
  II_G_336: XOR2 port map (
      O => UN2_COUNTFORHORIZONTAL_1(1),
      I0 => COUNTFORHORIZONTAL(0),
      I1 => COUNTFORHORIZONTAL(1));
  \II_countforhorizontal_0_5_.r\: INV port map (
      O => \COUNTFORHORIZONTAL_0_5_.UN3\,
      I0 => PIXELCLOCK);
  \II_countforhorizontal_0_5_.m\: AND2 port map (
      O => \COUNTFORHORIZONTAL_0_5_.UN1\,
      I0 => COUNTFORHORIZONTAL_3(5),
      I1 => PIXELCLOCK);
  \II_countforhorizontal_0_5_.n\: AND2 port map (
      O => \COUNTFORHORIZONTAL_0_5_.UN0\,
      I0 => COUNTFORHORIZONTAL(5),
      I1 => \COUNTFORHORIZONTAL