videogenerator.vhm

用lattice XP3 demo板设计的VGA信号发生器

      I1 => COUNTFORVERTICAL_3_I_0(11));
  II_un65_pixelclock_5: AND2 port map (
      O => N_635_5,
      I0 => N_635_1,
      I1 => N_635_2);
  II_un65_pixelclock_6: AND2 port map (
      O => N_635_6,
      I0 => N_635_3,
      I1 => N_635_4);
  II_un7_pixelclock_4_cZ: AND2 port map (
      O => UN7_PIXELCLOCK_4,
      I0 => UN7_PIXELCLOCK_1_0,
      I1 => UN7_PIXELCLOCK_2_0);
  II_un7_pixelclock_5_cZ: AND2 port map (
      O => UN7_PIXELCLOCK_5,
      I0 => UN7_PIXELCLOCK_3_0,
      I1 => UN2_COUNTFORHORIZONTAL_1(1));
  II_un7_pixelclock_cZ: AND2 port map (
      O => UN7_PIXELCLOCK,
      I0 => UN7_PIXELCLOCK_4,
      I1 => UN7_PIXELCLOCK_5);
  II_un25_pixelclock_1_0_cZ: AND2 port map (
      O => UN25_PIXELCLOCK_1_0,
      I0 => COUNTFORHORIZONTAL_3_I_0(5),
      I1 => COUNTFORHORIZONTAL_3_I_0(6));
  II_un25_pixelclock_2_cZ: AND2 port map (
      O => UN25_PIXELCLOCK_2,
      I0 => UN7_PIXELCLOCK_2,
      I1 => UN25_PIXELCLOCK_1);
  II_un25_pixelclock_3_cZ: AND2 port map (
      O => UN25_PIXELCLOCK_3,
      I0 => COUNTFORHORIZONTAL_3_I(0),
      I1 => COUNTFORHORIZONTAL_3_I(1));
  II_un25_pixelclock_4_cZ: AND2 port map (
      O => UN25_PIXELCLOCK_4,
      I0 => COUNTFORHORIZONTAL_3_I_0(3),
      I1 => COUNTFORHORIZONTAL_3_I_0(4));
  II_un25_pixelclock_5_cZ: AND2 port map (
      O => UN25_PIXELCLOCK_5,
      I0 => UN25_PIXELCLOCK_1_0,
      I1 => UN25_PIXELCLOCK_2);
  II_un25_pixelclock_6_cZ: AND2 port map (
      O => UN25_PIXELCLOCK_6,
      I0 => UN25_PIXELCLOCK_3,
      I1 => UN25_PIXELCLOCK_4);
  II_un25_pixelclock_cZ: AND2 port map (
      O => UN25_PIXELCLOCK,
      I0 => UN25_PIXELCLOCK_5,
      I1 => UN25_PIXELCLOCK_6);
  II_VGAv_2_sqmuxa_1_cZ: AND2 port map (
      O => VGAV_2_SQMUXA_1,
      I0 => UN25_PIXELCLOCK,
      I1 => UN29_PIXELCLOCK_I_0);
  II_VGAv_2_sqmuxa_cZ: AND2 port map (
      O => VGAV_2_SQMUXA,
      I0 => VGAV_2_SQMUXA_1,
      I1 => UN33_PIXELCLOCK);
  II_G_245_1: AND2 port map (
      O => UN11_PIXELCLOCK_I_0_1,
      I0 => UN2_COUNTFORHORIZONTAL_1_I(10),
      I1 => N_542_I_0);
  II_G_245_2: AND2 port map (
      O => UN11_PIXELCLOCK_I_0_2,
      I0 => N_309_I,
      I1 => N_530);
  II_G_245: AND2 port map (
      O => UN11_PIXELCLOCK_I_0,
      I0 => UN11_PIXELCLOCK_I_0_1,
      I1 => UN11_PIXELCLOCK_I_0_2);
  II_un77_pixelclock_0_a2: AND2 port map (
      O => UN77_PIXELCLOCK,
      I0 => N_556,
      I1 => COUNTFORPH_I_0(6));
  II_un7_pixelclock_1_cZ: AND2 port map (
      O => UN7_PIXELCLOCK_1,
      I0 => N_289,
      I1 => UN2_COUNTFORHORIZONTAL_1(6));
  II_un7_pixelclock_2_cZ: AND2 port map (
      O => UN7_PIXELCLOCK_2,
      I0 => N_542_I_0,
      I1 => UN2_COUNTFORHORIZONTAL_1_I_0(2));
  II_un25_pixelclock_1_cZ: AND2 port map (
      O => UN25_PIXELCLOCK_1,
      I0 => N_530,
      I1 => COUNTFORHORIZONTAL_3_I_0(10));
  II_G_232: AND2 port map (
      O => N_309,
      I0 => N_428_I,
      I1 => UN7_PIXELCLOCK_1);
  II_G_147_1: AND2 port map (
      O => UN51_PIXELCLOCK_1_I_0,
      I0 => N_547_I,
      I1 => UN25_PIXELCLOCK_1);
  II_un29_pixelclock_1_cZ: AND2 port map (
      O => UN29_PIXELCLOCK_1,
      I0 => UN1_COUNTFORVERTICAL_I_0(4),
      I1 => UN1_COUNTFORVERTICAL_I_0(7));
  II_un29_pixelclock_2_cZ: AND2 port map (
      O => UN29_PIXELCLOCK_2,
      I0 => UN1_COUNTFORVERTICAL_I_0(9),
      I1 => UN1_COUNTFORVERTICAL_I_0(12));
  \II_countforph_4_i_a2_1[3]\: AND2 port map (
      O => N_556_1,
      I0 => N_397,
      I1 => COUNTFORPH(2));
  \II_countforph_4_i_a2_2[3]\: AND2 port map (
      O => N_556_2,
      I0 => UN1_COUNTFORPH_I_0(5),
      I1 => UN1_COUNTFORPH_I_0(6));
  \II_countforph_4_i_a2_3[3]\: AND2 port map (
      O => N_556_3,
      I0 => N_556_1,
      I1 => N_556_2);
  \II_countforph_4_i_a2[3]\: AND2 port map (
      O => N_556,
      I0 => N_556_3,
      I1 => UN1_COUNTFORPH_I_0(4));
  II_un7_pixelclock_1_0_cZ: AND2 port map (
      O => UN7_PIXELCLOCK_1_0,
      I0 => UN2_COUNTFORHORIZONTAL_1(10),
      I1 => UN7_PIXELCLOCK_3);
  II_un7_pixelclock_2_0_cZ: AND2 port map (
      O => UN7_PIXELCLOCK_2_0,
      I0 => N_530,
      I1 => UN7_PIXELCLOCK_1);
  II_un7_pixelclock_3_0_cZ: AND2 port map (
      O => UN7_PIXELCLOCK_3_0,
      I0 => UN7_PIXELCLOCK_2,
      I1 => COUNTFORHORIZONTAL_I_0(0));
  II_N_136_i_cZ: INV port map (
      O => N_136_I,
      I0 => N_136);
  II_G_90_i: INV port map (
      O => N_139,
      I0 => N_639);
  II_N_130_i_cZ: INV port map (
      O => N_130_I,
      I0 => N_130);
  II_G_86_i: INV port map (
      O => N_135,
      I0 => N_640);
  \II_countforhorizontal_3_i_cZ[0]\: INV port map (
      O => COUNTFORHORIZONTAL_3_I(0),
      I0 => COUNTFORHORIZONTAL_3(0));
  \II_countforhorizontal_3_i_cZ[1]\: INV port map (
      O => COUNTFORHORIZONTAL_3_I(1),
      I0 => COUNTFORHORIZONTAL_3(1));
  II_VGAh_cs_i_m_i_cZ: INV port map (
      O => VGAH_CS_I_M_I,
      I0 => VGAH_CS_I_M);
  II_VGAv_c_i_cZ: INV port map (
      O => VGAV_C_I,
      I0 => VGAV_C);
  II_VGAv_2_sqmuxa_i_cZ: INV port map (
      O => VGAV_2_SQMUXA_I,
      I0 => VGAV_2_SQMUXA);
  II_VGAv_2_f1_i: INV port map (
      O => VGAV_2_F1,
      I0 => N_643);
  II_N_309_i_cZ: INV port map (
      O => N_309_I,
      I0 => N_309);
  II_G_245_i: INV port map (
      O => UN11_PIXELCLOCK,
      I0 => UN11_PIXELCLOCK_I_0);
  II_G_182_i: INV port map (
      O => N_231,
      I0 => N_647);
  \II_un2_countforhorizontal_1_i_cZ[10]\: INV port map (
      O => UN2_COUNTFORHORIZONTAL_1_I(10),
      I0 => UN2_COUNTFORHORIZONTAL_1(10));
  II_N_556_i_cZ: INV port map (
      O => N_556_I,
      I0 => N_556);
  II_G_80_i: INV port map (
      O => N_129,
      I0 => N_622);
  \II_un1_countforvertical_i_cZ[6]\: INV port map (
      O => UN1_COUNTFORVERTICAL_I(6),
      I0 => UN1_COUNTFORVERTICAL(6));
  \II_un1_countforvertical_i_cZ[8]\: INV port map (
      O => UN1_COUNTFORVERTICAL_I(8),
      I0 => UN1_COUNTFORVERTICAL(8));
  \II_un1_countforvertical_i_cZ[11]\: INV port map (
      O => UN1_COUNTFORVERTICAL_I(11),
      I0 => UN1_COUNTFORVERTICAL(11));
  \II_un1_countforvertical_i_cZ[10]\: INV port map (
      O => UN1_COUNTFORVERTICAL_I(10),
      I0 => UN1_COUNTFORVERTICAL(10));
  II_VGAdena_0_sqmuxa_1_i_cZ: INV port map (
      O => VGADENA_0_SQMUXA_1_I,
      I0 => VGADENA_0_SQMUXA_1);
  II_N_1_i_cZ: INV port map (
      O => N_1_I,
      I0 => N_1);
  II_VGAdena_1_i: INV port map (
      O => N_49,
      I0 => N_627);
  II_N_547_i_cZ: INV port map (
      O => N_547_I,
      I0 => N_547);
  II_N_11_i_cZ: INV port map (
      O => N_11_I,
      I0 => N_11);
  II_G_49_i: INV port map (
      O => UN63_PIXELCLOCK,
      I0 => UN63_PIXELCLOCK_I_0);
  II_G_147_1_i: INV port map (
      O => UN51_PIXELCLOCK_1,
      I0 => UN51_PIXELCLOCK_1_I_0);
  II_un65_pixelclock_i: INV port map (
      O => UN65_PIXELCLOCK,
      I0 => N_635);
  II_N_238_i_cZ: INV port map (
      O => N_238_I,
      I0 => N_238);
  II_G_192_i: INV port map (
      O => N_241,
      I0 => N_636);
  \II_un1_countforvertical_i_cZ[3]\: INV port map (
      O => UN1_COUNTFORVERTICAL_I(3),
      I0 => UN1_COUNTFORVERTICAL(3));
  \II_un1_countforvertical_i_cZ[2]\: INV port map (
      O => UN1_COUNTFORVERTICAL_I(2),
      I0 => UN1_COUNTFORVERTICAL(2));
  \II_un1_countforvertical_i_cZ[5]\: INV port map (
      O => UN1_COUNTFORVERTICAL_I(5),
      I0 => UN1_COUNTFORVERTICAL(5));
  II_N_348_i_cZ: INV port map (
      O => N_348_I,
      I0 => N_348);
  II_G_294_i: INV port map (
      O => UN33_PIXELCLOCK,
      I0 => UN33_PIXELCLOCK_I_0);
  II_G_76_i: INV port map (
      O => N_125,
      I0 => N_618);
  \II_countforvertical_3_i_cZ[2]\: INV port map (
      O => COUNTFORVERTICAL_3_I(2),
      I0 => COUNTFORVERTICAL_3(2));
  \II_countforvertical_3_i_cZ[5]\: INV port map (
      O => COUNTFORVERTICAL_3_I(5),
      I0 => COUNTFORVERTICAL_3(5));
  II_N_129_1_i_cZ: INV port map (
      O => N_129_1_I,
      I0 => N_129_1);
  \II_countforvertical_3_0_8_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_0_8_.UN3\,
      I0 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_8_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_8_.UN1\,
      I0 => UN1_COUNTFORVERTICAL(8),
      I1 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_8_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_8_.UN0\,
      I0 => COUNTFORVERTICAL(8),
      I1 => \COUNTFORVERTICAL_3_0_8_.UN3\);
  \II_countforvertical_3_0_8_.p\: OR2 port map (
      O => N_255,
      I0 => \COUNTFORVERTICAL_3_0_8_.UN1\,
      I1 => \COUNTFORVERTICAL_3_0_8_.UN0\);
  \II_countforvertical_3_0_6_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_0_6_.UN3\,
      I0 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_6_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_6_.UN1\,
      I0 => UN1_COUNTFORVERTICAL(6),
      I1 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_6_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_6_.UN0\,
      I0 => COUNTFORVERTICAL(6),
      I1 => \COUNTFORVERTICAL_3_0_6_.UN3\);
  \II_countforvertical_3_0_6_.p\: OR2 port map (
      O => N_253,
      I0 => \COUNTFORVERTICAL_3_0_6_.UN1\,
      I1 => \COUNTFORVERTICAL_3_0_6_.UN0\);
  \II_countforvertical_3_0_5_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_0_5_.UN3\,
      I0 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_5_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_5_.UN1\,
      I0 => UN1_COUNTFORVERTICAL(5),
      I1 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_5_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_5_.UN0\,
      I0 => COUNTFORVERTICAL(5),
      I1 => \COUNTFORVERTICAL_3_0_5_.UN3\);
  \II_countforvertical_3_0_5_.p\: OR2 port map (
      O => N_252,
      I0 => \COUNTFORVERTICAL_3_0_5_.UN1\,
      I1 => \COUNTFORVERTICAL_3_0_5_.UN0\);
  \II_countforvertical_3_0_4_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_0_4_.UN3\,
      I0 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_4_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_4_.UN1\,
      I0 => UN1_COUNTFORVERTICAL(4),
      I1 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_4_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_4_.UN0\,
      I0 => COUNTFORVERTICAL(4),
      I1 => \COUNTFORVERTICAL_3_0_4_.UN3\);
  \II_countforvertical_3_0_4_.p\: OR2 port map (
      O => COUNTFORVERTICAL_3(4),
      I0 => \COUNTFORVERTICAL_3_0_4_.UN1\,
      I1 => \COUNTFORVERTICAL_3_0_4_.UN0\);
  \II_countforvertical_3_0_3_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_0_3_.UN3\,
      I0 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_3_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_3_.UN1\,
      I0 => UN1_COUNTFORVERTICAL(3),
      I1 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_3_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_3_.UN0\,
      I0 => COUNTFORVERTICAL(3),
      I1 => \COUNTFORVERTICAL_3_0_3_.UN3\);
  \II_countforvertical_3_0_3_.p\: OR2 port map (
      O => N_250,
      I0 => \COUNTFORVERTICAL_3_0_3_.UN1\,
      I1 => \COUNTFORVERTICAL_3_0_3_.UN0\);
  \II_countforvertical_3_0_2_.r\: INV port map (
      O => \COUNTFORVERTICAL_3_0_2_.UN3\,
      I0 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_2_.m\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_2_.UN1\,
      I0 => UN1_COUNTFORVERTICAL(2),
      I1 => UN25_PIXELCLOCK);
  \II_countforvertical_3_0_2_.n\: AND2 port map (
      O => \COUNTFORVERTICAL_3_0_2_.UN0\,
      I0 => COUNTFORVERTICAL(2),
      I1 => \COUNTFORVERTICAL_3_0_2_.UN3\);
  \II_countforvertical_3_0_2_.p\: OR2 port map (
      O => N_249,
      I0 => \COUNTFORVERTICAL_3_0_2_.UN1\,
      I1 => \COUNTFORVERTICAL_3_0_2_.UN0\);
  II_G_386: AND2 port map (
      O => N_474,
      I0 => N_471,
      I1 => COUNTFORVERTICAL(6));
  II_G_385: XOR2 port map (
      O => UN1_COUNTFORVERTICAL(6),
      I0 => N_471,
      I1 => COUNTFORVERTICAL(6));
  II_G_384: AND2 port map (
      O => N_471,
      I0 => N_468,
      I1 => COUNTFORVERTICAL(5));
  II_G_383: XOR2 port map (
      O => UN1_COUNTFORVERTICAL(5),
      I0 => N_468,
      I1 => COUNTFORVERTICAL(5));
  II_G_380: AND2 port map (
      O => N_465,
      I0 => N_462,
      I1 => COUNTFORVERTICAL(3));
  II_G_379: XOR2 port map (
      O => UN1_COUNTFORVERTICAL(3),
      I0 => N_462,
      I1 => COUNTFORVERTICAL(3));
  II_N_428_i_cZ: INV port map (
      O => N_428_I,
      I0 => N_428);
  II_G_390: AND2 port map (
      O => N_480,
      I0 => N_477,
      I1 => COUNTFORVERTICAL(8));
  II_G_389: XOR2 port map (
      O => UN1_COUNTFORVERTICAL(8),
      I0 => N_477,
      I1 => COUNTFORVERTICAL(8));
  II_G_382: AND2 port map (
      O => N_468,
      I0 => N_465,
      I1 => COUNTFORVERTICAL(4));
  II_G_381: XOR2 port map (
      O => UN1_COUNTFORVERTICAL(4),
      I0 => N_465,
      I1 => COUNTFORVERTICAL(4));
  \II_countforvertical_3_i[4]\: INV port map (
      O => COUNTFORVERTICAL_3_I_0(4),
      I0 => COUNTFORVERTICAL_3(4));
  II_G_81: AND2 port map (
      O => N_130,
      I0 => N_129,
      I1 => COUNTFORVERTICAL_3_I_0(4));