videogenerator.vhm

用lattice XP3 demo板设计的VGA信号发生器

      D => N_37,
      CLK => CLK_I_0);
  \II_countforcolor_cZ[2]\: DFF port map (
      Q => COUNTFORCOLOR(2),
      D => N_38,
      CLK => CLK_I_0);
  \II_countforcolor_cZ[3]\: DFF port map (
      Q => COUNTFORCOLOR(3),
      D => N_39,
      CLK => CLK_I_0);
  \II_countforcolor_cZ[4]\: DFF port map (
      Q => COUNTFORCOLOR(4),
      D => N_40,
      CLK => CLK_I_0);
  \II_countforcolor_cZ[5]\: DFF port map (
      Q => COUNTFORCOLOR(5),
      D => N_41,
      CLK => CLK_I_0);
  \II_countforhorizontal_cZ[4]\: DFF port map (
      Q => COUNTFORHORIZONTAL(4),
      D => N_27,
      CLK => CLK_I_0);
  \II_countforhorizontal_cZ[5]\: DFF port map (
      Q => COUNTFORHORIZONTAL(5),
      D => N_28,
      CLK => CLK_I_0);
  \II_countforhorizontal_cZ[6]\: DFF port map (
      Q => COUNTFORHORIZONTAL(6),
      D => N_29,
      CLK => CLK_I_0);
  \II_countforhorizontal_cZ[7]\: DFF port map (
      Q => COUNTFORHORIZONTAL(7),
      D => N_30,
      CLK => CLK_I_0);
  \II_countforhorizontal_cZ[8]\: DFF port map (
      Q => COUNTFORHORIZONTAL(8),
      D => N_31,
      CLK => CLK_I_0);
  \II_countforhorizontal_cZ[9]\: DFF port map (
      Q => COUNTFORHORIZONTAL(9),
      D => N_32,
      CLK => CLK_I_0);
  \II_countforhorizontal_cZ[10]\: DFF port map (
      Q => COUNTFORHORIZONTAL(10),
      D => N_33,
      CLK => CLK_I_0);
  \II_countforhorizontal_cZ[11]\: DFF port map (
      Q => COUNTFORHORIZONTAL(11),
      D => N_34,
      CLK => CLK_I_0);
  \II_countforhorizontal_cZ[12]\: DFF port map (
      Q => COUNTFORHORIZONTAL(12),
      D => N_35,
      CLK => CLK_I_0);
  \II_VGArDFF[1]\: DFF port map (
      Q => VGAR_C(1),
      D => N_18,
      CLK => CLK_I_0);
  \II_VGAgDFF[0]\: DFF port map (
      Q => VGAG_C(0),
      D => N_19,
      CLK => CLK_I_0);
  \II_VGAgDFF[1]\: DFF port map (
      Q => VGAG_C(1),
      D => N_20,
      CLK => CLK_I_0);
  \II_VGAbDFF[0]\: DFF port map (
      Q => VGAB_C(0),
      D => N_21,
      CLK => CLK_I_0);
  \II_VGAbDFF[1]\: DFF port map (
      Q => VGAB_C(1),
      D => N_22,
      CLK => CLK_I_0);
  \II_countforhorizontal_cZ[0]\: DFF port map (
      Q => COUNTFORHORIZONTAL(0),
      D => N_23,
      CLK => CLK_I_0);
  \II_countforhorizontal_cZ[1]\: DFF port map (
      Q => COUNTFORHORIZONTAL(1),
      D => N_24,
      CLK => CLK_I_0);
  \II_countforhorizontal_cZ[2]\: DFF port map (
      Q => COUNTFORHORIZONTAL(2),
      D => N_25,
      CLK => CLK_I_0);
  \II_countforhorizontal_cZ[3]\: DFF port map (
      Q => COUNTFORHORIZONTAL(3),
      D => N_26,
      CLK => CLK_I_0);
  \II_countforvertical_cZ[12]\: DFF port map (
      Q => COUNTFORVERTICAL(12),
      D => N_15,
      CLK => CLK_I_0);
  \II_VGArDFF[0]\: DFF port map (
      Q => VGAR_C(0),
      D => N_17,
      CLK => CLK_I_0);
  \II_countforvertical_cZ[0]\: DFF port map (
      Q => COUNTFORVERTICAL(0),
      D => N_3,
      CLK => CLK_I_0);
  \II_countforvertical_cZ[1]\: DFF port map (
      Q => COUNTFORVERTICAL(1),
      D => N_4,
      CLK => CLK_I_0);
  \II_countforvertical_cZ[2]\: DFF port map (
      Q => COUNTFORVERTICAL(2),
      D => N_5,
      CLK => CLK_I_0);
  \II_countforvertical_cZ[3]\: DFF port map (
      Q => COUNTFORVERTICAL(3),
      D => N_6,
      CLK => CLK_I_0);
  \II_countforvertical_cZ[4]\: DFF port map (
      Q => COUNTFORVERTICAL(4),
      D => N_7,
      CLK => CLK_I_0);
  \II_countforvertical_cZ[5]\: DFF port map (
      Q => COUNTFORVERTICAL(5),
      D => N_8,
      CLK => CLK_I_0);
  \II_countforvertical_cZ[6]\: DFF port map (
      Q => COUNTFORVERTICAL(6),
      D => N_9,
      CLK => CLK_I_0);
  \II_countforvertical_cZ[7]\: DFF port map (
      Q => COUNTFORVERTICAL(7),
      D => N_10,
      CLK => CLK_I_0);
  \II_countforvertical_cZ[8]\: DFF port map (
      Q => COUNTFORVERTICAL(8),
      D => N_11,
      CLK => CLK_I_0);
  \II_countforvertical_cZ[9]\: DFF port map (
      Q => COUNTFORVERTICAL(9),
      D => N_12,
      CLK => CLK_I_0);
  \II_countforvertical_cZ[10]\: DFF port map (
      Q => COUNTFORVERTICAL(10),
      D => N_13,
      CLK => CLK_I_0);
  \II_countforvertical_cZ[11]\: DFF port map (
      Q => COUNTFORVERTICAL(11),
      D => N_14,
      CLK => CLK_I_0);
  II_VGAvDFF: DFF port map (
      Q => VGAV_C,
      D => N_2,
      CLK => CLK_I_0);
  II_VGAh_csDFF: DFF port map (
      Q => VGAH_CS_C,
      D => N_16,
      CLK => CLK_I_0);
  II_VGAdenaDFF: DFF port map (
      Q => VGADENA_C,
      D => N_49,
      CLK => CLK_I_0);
  II_pixelClock_cZ: DFF port map (
      Q => PIXELCLOCK,
      D => PIXELCLOCK_I_0,
      CLK => CLK_I_0);
  II_clk_cZ: IBUF port map (
      O => CLK_C,
      I0 => clk);
  II_UARTtx_cZ: OBUF port map (
      O => UARTtx,
      I0 => GND);
  \II_VGAr_cZ[0]\: OBUF port map (
      O => VGAr(0),
      I0 => VGAR_C(0));
  \II_VGAr_cZ[1]\: OBUF port map (
      O => VGAr(1),
      I0 => VGAR_C(1));
  \II_VGAg_cZ[0]\: OBUF port map (
      O => VGAg(0),
      I0 => VGAG_C(0));
  \II_VGAg_cZ[1]\: OBUF port map (
      O => VGAg(1),
      I0 => VGAG_C(1));
  \II_VGAb_cZ[0]\: OBUF port map (
      O => VGAb(0),
      I0 => VGAB_C(0));
  \II_VGAb_cZ[1]\: OBUF port map (
      O => VGAb(1),
      I0 => VGAB_C(1));
  II_VGAh_cs_cZ: OBUF port map (
      O => VGAh_cs,
      I0 => VGAH_CS_C);
  II_VGAv_cZ: OBUF port map (
      O => VGAv,
      I0 => VGAV_C);
  II_VGAdena_cZ: OBUF port map (
      O => VGAdena,
      I0 => VGADENA_C);
  \II_NUMlocation_cZ[0]\: OBUF port map (
      O => NUMlocation(0),
      I0 => GND);
  \II_NUMlocation_cZ[1]\: OBUF port map (
      O => NUMlocation(1),
      I0 => GND);
  \II_NUMlocation_cZ[2]\: OBUF port map (
      O => NUMlocation(2),
      I0 => GND);
  \II_NUMlocation_cZ[3]\: OBUF port map (
      O => NUMlocation(3),
      I0 => GND);
  \II_NUMdata_cZ[0]\: OBUF port map (
      O => NUMdata(0),
      I0 => GND);
  \II_NUMdata_cZ[1]\: OBUF port map (
      O => NUMdata(1),
      I0 => GND);
  \II_NUMdata_cZ[2]\: OBUF port map (
      O => NUMdata(2),
      I0 => GND);
  \II_NUMdata_cZ[3]\: OBUF port map (
      O => NUMdata(3),
      I0 => GND);
  \II_NUMdata_cZ[4]\: OBUF port map (
      O => NUMdata(4),
      I0 => GND);
  \II_NUMdata_cZ[5]\: OBUF port map (
      O => NUMdata(5),
      I0 => GND);
  \II_NUMdata_cZ[6]\: OBUF port map (
      O => NUMdata(6),
      I0 => GND);
  \II_NUMdata_cZ[7]\: OBUF port map (
      O => NUMdata(7),
      I0 => GND);
  II_un29_pixelclock_8_cZ: AND2 port map (
      O => UN29_PIXELCLOCK_8,
      I0 => UN29_PIXELCLOCK_6,
      I1 => UN29_PIXELCLOCK_7);
  II_un29_pixelclock_cZ: AND2 port map (
      O => UN29_PIXELCLOCK,
      I0 => UN29_PIXELCLOCK_8,
      I1 => UN29_PIXELCLOCK_5);
  II_G_294_1: AND2 port map (
      O => UN33_PIXELCLOCK_I_0_1,
      I0 => UN1_COUNTFORVERTICAL_I(6),
      I1 => UN1_COUNTFORVERTICAL_I(8));
  II_G_294_2: AND2 port map (
      O => UN33_PIXELCLOCK_I_0_2,
      I0 => UN29_PIXELCLOCK_2,
      I1 => N_348_I);
  II_G_294_3: AND2 port map (
      O => UN33_PIXELCLOCK_I_0_3,
      I0 => UN1_COUNTFORVERTICAL_I(2),
      I1 => UN1_COUNTFORVERTICAL_I(3));
  II_G_294_4: AND2 port map (
      O => UN33_PIXELCLOCK_I_0_4,
      I0 => UN29_PIXELCLOCK_1_0,
      I1 => UN33_PIXELCLOCK_I_0_1);
  II_G_294_5: AND2 port map (
      O => UN33_PIXELCLOCK_I_0_5,
      I0 => UN33_PIXELCLOCK_I_0_2,
      I1 => UN33_PIXELCLOCK_I_0_3);
  II_G_294_6_0: AND2 port map (
      O => UN33_PIXELCLOCK_I_0_6,
      I0 => UN33_PIXELCLOCK_I_0_4,
      I1 => UN33_PIXELCLOCK_I_0_5);
  II_G_294: AND2 port map (
      O => UN33_PIXELCLOCK_I_0,
      I0 => UN33_PIXELCLOCK_I_0_6,
      I1 => UN1_COUNTFORVERTICAL_I(5));
  \II_countforph_4_i_1[3]\: AND2 port map (
      O => N_555_I_0_1,
      I0 => N_556_I,
      I1 => VGADENA_I_0);
  \II_countforph_4_i[3]\: AND2 port map (
      O => N_555_I_0,
      I0 => N_555_I_0_1,
      I1 => UN1_COUNTFORPH(3));
  II_un65_pixelclock_7: AND2 port map (
      O => N_635_7,
      I0 => N_635_5,
      I1 => N_635_6);
  II_un65_pixelclock_cZ: AND2 port map (
      O => N_635,
      I0 => N_635_7,
      I1 => COUNTFORVERTICAL_3_I_0(12));
  II_G_49_1: AND2 port map (
      O => UN63_PIXELCLOCK_I_0_1,
      I0 => N_11_I,
      I1 => COUNTFORVERTICAL_3_I(2));
  II_G_49_2: AND2 port map (
      O => UN63_PIXELCLOCK_I_0_2,
      I0 => COUNTFORVERTICAL_3_I(5),
      I1 => COUNTFORVERTICAL_3_I_0(3));
  II_G_49_3: AND2 port map (
      O => UN63_PIXELCLOCK_I_0_3,
      I0 => COUNTFORVERTICAL_3_I_0(7),
      I1 => COUNTFORVERTICAL_3_I_0(4));
  II_G_49_4: AND2 port map (
      O => UN63_PIXELCLOCK_I_0_4,
      I0 => UN63_PIXELCLOCK_I_0_1,
      I1 => UN63_PIXELCLOCK_I_0_2);
  II_G_49_5: AND2 port map (
      O => UN63_PIXELCLOCK_I_0_5,
      I0 => UN63_PIXELCLOCK_I_0_3,
      I1 => COUNTFORVERTICAL_3_I_0(6));
  II_G_49: AND2 port map (
      O => UN63_PIXELCLOCK_I_0,
      I0 => UN63_PIXELCLOCK_I_0_4,
      I1 => UN63_PIXELCLOCK_I_0_5);
  II_un29_pixelclock_1_0_cZ: AND2 port map (
      O => UN29_PIXELCLOCK_1_0,
      I0 => UN33_PIXELCLOCK_6_I_0,
      I1 => UN29_PIXELCLOCK_1);
  II_un29_pixelclock_2_0_cZ: AND2 port map (
      O => UN29_PIXELCLOCK_2_0,
      I0 => UN1_COUNTFORVERTICAL(6),
      I1 => UN1_COUNTFORVERTICAL(8));
  II_un29_pixelclock_3_cZ: AND2 port map (
      O => UN29_PIXELCLOCK_3,
      I0 => UN1_COUNTFORVERTICAL_I_0(1),
      I1 => UN29_PIXELCLOCK_2);
  II_un29_pixelclock_4_cZ: AND2 port map (
      O => UN29_PIXELCLOCK_4,
      I0 => COUNTFORVERTICAL(0),
      I1 => COUNTFORVERTICAL_I_0(2));
  II_un29_pixelclock_5_cZ: AND2 port map (
      O => UN29_PIXELCLOCK_5,
      I0 => UN1_COUNTFORVERTICAL(3),
      I1 => UN1_COUNTFORVERTICAL(5));
  II_un29_pixelclock_6_cZ: AND2 port map (
      O => UN29_PIXELCLOCK_6,
      I0 => UN29_PIXELCLOCK_1_0,
      I1 => UN29_PIXELCLOCK_2_0);
  II_un29_pixelclock_7_cZ: AND2 port map (
      O => UN29_PIXELCLOCK_7,
      I0 => UN29_PIXELCLOCK_3,
      I1 => UN29_PIXELCLOCK_4);
  II_G_86_1: AND2 port map (
      O => N_640_1,
      I0 => N_130_I,
      I1 => N_252);
  II_G_86: AND2 port map (
      O => N_640,
      I0 => N_640_1,
      I1 => COUNTFORVERTICAL_3(6));
  II_G_134_1: AND2 port map (
      O => N_547_1,
      I0 => N_422_I_0,
      I1 => COUNTFORHORIZONTAL_3(4));
  II_G_134_2: AND2 port map (
      O => N_547_2,
      I0 => N_647,
      I1 => COUNTFORHORIZONTAL_3(6));
  II_G_134: AND2 port map (
      O => N_547,
      I0 => N_547_1,
      I1 => N_547_2);
  II_G_189_1: AND2 port map (
      O => N_238_1,
      I0 => N_231,
      I1 => COUNTFORHORIZONTAL_3_I_0(6));
  II_G_189: AND2 port map (
      O => N_238,
      I0 => N_530,
      I1 => N_238_1);
  II_VGAdena_0_sqmuxa_1_0_cZ: AND2 port map (
      O => VGADENA_0_SQMUXA_1_0,
      I0 => VGAH_CS_C,
      I1 => VGAV_C);
  II_VGAdena_0_sqmuxa_cZ: AND2 port map (
      O => VGADENA_0_SQMUXA,
      I0 => VGADENA_0_SQMUXA_1_0,
      I1 => PIXELCLOCK);
  II_un65_pixelclock_1: AND2 port map (
      O => N_635_1,
      I0 => UN51_PIXELCLOCK_1,
      I1 => UN63_PIXELCLOCK);
  II_un65_pixelclock_2: AND2 port map (
      O => N_635_2,
      I0 => N_542_I_0,
      I1 => N_139);
  II_un65_pixelclock_3: AND2 port map (
      O => N_635_3,
      I0 => N_241,
      I1 => COUNTFORVERTICAL_3_I_0(9));
  II_un65_pixelclock_4: AND2 port map (
      O => N_635_4,
      I0 => COUNTFORVERTICAL_3_I_0(10),