videogenerator.vhm

用lattice XP3 demo板设计的VGA信号发生器

  signal VGADENA_I_0 : std_logic ;
  signal N_422_I_0 : std_logic ;
  signal VGAH_CS_I_0 : std_logic ;
  signal VGAV_1_SQMUXA_I_0 : std_logic ;
  signal UN29_PIXELCLOCK_I_0 : std_logic ;
  signal PIXELCLOCK_I_0 : std_logic ;
  signal CLK_I_0 : std_logic ;
  signal CLK_C : std_logic ;
  signal VGAH_CS_C : std_logic ;
  signal VGAV_C : std_logic ;
  signal VGADENA_C : std_logic ;
  signal N_348_I : std_logic ;
  signal UN33_PIXELCLOCK_I_0 : std_logic ;
  signal N_618 : std_logic ;
  signal N_129_1_I : std_logic ;
  signal N_622 : std_logic ;
  signal UN33_PIXELCLOCK_6_I_0 : std_logic ;
  signal VGADENA_0_SQMUXA_1_I : std_logic ;
  signal N_1_I : std_logic ;
  signal N_627 : std_logic ;
  signal N_542_I_0 : std_logic ;
  signal N_547_I : std_logic ;
  signal N_11_I : std_logic ;
  signal UN63_PIXELCLOCK_I_0 : std_logic ;
  signal UN51_PIXELCLOCK_1_I_0 : std_logic ;
  signal N_635 : std_logic ;
  signal N_238_I : std_logic ;
  signal N_636 : std_logic ;
  signal N_136_I : std_logic ;
  signal N_639 : std_logic ;
  signal N_130_I : std_logic ;
  signal N_640 : std_logic ;
  signal VGAH_CS_I_M_I : std_logic ;
  signal VGAH_CS_3_IV_I_0 : std_logic ;
  signal VGAV_C_I : std_logic ;
  signal VGAV_2_SQMUXA_I : std_logic ;
  signal N_643 : std_logic ;
  signal N_309_I : std_logic ;
  signal UN11_PIXELCLOCK_I_0 : std_logic ;
  signal N_647 : std_logic ;
  signal N_541_I_0 : std_logic ;
  signal N_556_I : std_logic ;
  signal N_555_I_0 : std_logic ;
  signal UN7_PIXELCLOCK_1 : std_logic ;
  signal UN7_PIXELCLOCK_2 : std_logic ;
  signal UN25_PIXELCLOCK_1 : std_logic ;
  signal UN29_PIXELCLOCK_1 : std_logic ;
  signal UN29_PIXELCLOCK_2 : std_logic ;
  signal N_556_1 : std_logic ;
  signal N_556_2 : std_logic ;
  signal N_556_3 : std_logic ;
  signal UN7_PIXELCLOCK_1_0 : std_logic ;
  signal UN7_PIXELCLOCK_2_0 : std_logic ;
  signal UN7_PIXELCLOCK_3_0 : std_logic ;
  signal UN7_PIXELCLOCK_4 : std_logic ;
  signal UN7_PIXELCLOCK_5 : std_logic ;
  signal UN25_PIXELCLOCK_1_0 : std_logic ;
  signal UN25_PIXELCLOCK_2 : std_logic ;
  signal UN25_PIXELCLOCK_3 : std_logic ;
  signal UN25_PIXELCLOCK_4 : std_logic ;
  signal UN25_PIXELCLOCK_5 : std_logic ;
  signal UN25_PIXELCLOCK_6 : std_logic ;
  signal VGAV_2_SQMUXA_1 : std_logic ;
  signal UN11_PIXELCLOCK_I_0_1 : std_logic ;
  signal UN11_PIXELCLOCK_I_0_2 : std_logic ;
  signal N_640_1 : std_logic ;
  signal N_547_1 : std_logic ;
  signal N_547_2 : std_logic ;
  signal N_238_1 : std_logic ;
  signal VGADENA_0_SQMUXA_1_0 : std_logic ;
  signal N_635_1 : std_logic ;
  signal N_635_2 : std_logic ;
  signal N_635_3 : std_logic ;
  signal N_635_4 : std_logic ;
  signal N_635_5 : std_logic ;
  signal N_635_6 : std_logic ;
  signal N_635_7 : std_logic ;
  signal UN63_PIXELCLOCK_I_0_1 : std_logic ;
  signal UN63_PIXELCLOCK_I_0_2 : std_logic ;
  signal UN63_PIXELCLOCK_I_0_3 : std_logic ;
  signal UN63_PIXELCLOCK_I_0_4 : std_logic ;
  signal UN63_PIXELCLOCK_I_0_5 : std_logic ;
  signal UN29_PIXELCLOCK_1_0 : std_logic ;
  signal UN29_PIXELCLOCK_2_0 : std_logic ;
  signal UN29_PIXELCLOCK_3 : std_logic ;
  signal UN29_PIXELCLOCK_4 : std_logic ;
  signal UN29_PIXELCLOCK_5 : std_logic ;
  signal UN29_PIXELCLOCK_6 : std_logic ;
  signal UN29_PIXELCLOCK_7 : std_logic ;
  signal UN29_PIXELCLOCK_8 : std_logic ;
  signal UN33_PIXELCLOCK_I_0_1 : std_logic ;
  signal UN33_PIXELCLOCK_I_0_2 : std_logic ;
  signal UN33_PIXELCLOCK_I_0_3 : std_logic ;
  signal UN33_PIXELCLOCK_I_0_4 : std_logic ;
  signal UN33_PIXELCLOCK_I_0_5 : std_logic ;
  signal UN33_PIXELCLOCK_I_0_6 : std_logic ;
  signal N_555_I_0_1 : std_logic ;
  signal \COUNTFORVERTICAL_3_0_8_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_8_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_8_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_6_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_6_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_6_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_5_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_5_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_5_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_4_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_4_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_4_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_3_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_3_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_3_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_2_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_2_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_2_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_0_4_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_0_4_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_0_4_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_8_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_8_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_8_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_6_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_6_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_6_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_5_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_5_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_5_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_3_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_3_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_3_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_2_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_2_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_2_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_12_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_12_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_12_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_7_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_7_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_7_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_0_2_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_0_2_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_0_2_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_0_3_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_0_3_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_0_3_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_0_5_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_0_5_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_0_5_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_0_6_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_0_6_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_0_6_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_1_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_1_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_1_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_9_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_9_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_9_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_11_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_11_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_11_.UN0\ : std_logic ;
  signal \VGAH_CS_0.UN3\ : std_logic ;
  signal \VGAH_CS_0.UN1\ : std_logic ;
  signal \VGAH_CS_0.UN0\ : std_logic ;
  signal \VGAV_0.UN3\ : std_logic ;
  signal \VGAV_0.UN1\ : std_logic ;
  signal \VGAV_0.UN0\ : std_logic ;
  signal \VGADENA_0.UN3\ : std_logic ;
  signal \VGADENA_0.UN1\ : std_logic ;
  signal \VGADENA_0.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_5_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_5_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_5_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_1_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_1_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_1_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_0_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_0_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_0_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_11_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_11_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_11_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_0_0_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_0_0_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_0_0_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_0_1_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_0_1_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_0_1_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_3_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_3_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_3_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_12_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_12_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_12_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_0_12_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_0_12_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_0_12_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_0_11_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_0_11_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_0_11_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_0_7_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_0_7_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_0_7_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_0_8_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_0_8_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_0_8_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_10_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_10_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_10_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_10_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_10_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_3_0_10_.UN0\ : std_logic ;
  signal \COUNTFORCOLOR_0_1_.UN3\ : std_logic ;
  signal \COUNTFORCOLOR_0_1_.UN1\ : std_logic ;
  signal \COUNTFORCOLOR_0_1_.UN0\ : std_logic ;
  signal \COUNTFORCOLOR_0_2_.UN3\ : std_logic ;
  signal \COUNTFORCOLOR_0_2_.UN1\ : std_logic ;
  signal \COUNTFORCOLOR_0_2_.UN0\ : std_logic ;
  signal \COUNTFORCOLOR_0_3_.UN3\ : std_logic ;
  signal \COUNTFORCOLOR_0_3_.UN1\ : std_logic ;
  signal \COUNTFORCOLOR_0_3_.UN0\ : std_logic ;
  signal \COUNTFORCOLOR_0_4_.UN3\ : std_logic ;
  signal \COUNTFORCOLOR_0_4_.UN1\ : std_logic ;
  signal \COUNTFORCOLOR_0_4_.UN0\ : std_logic ;
  signal \COUNTFORCOLOR_0_5_.UN3\ : std_logic ;
  signal \COUNTFORCOLOR_0_5_.UN1\ : std_logic ;
  signal \COUNTFORCOLOR_0_5_.UN0\ : std_logic ;
  signal \COUNTFORPH_0_3_.UN3\ : std_logic ;
  signal \COUNTFORPH_0_3_.UN1\ : std_logic ;
  signal \COUNTFORPH_0_3_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_0_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_0_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_0_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_10_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_10_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_10_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_0_9_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_0_9_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_0_9_.UN0\ : std_logic ;
  signal \COUNTFORVERTICAL_0_10_.UN3\ : std_logic ;
  signal \COUNTFORVERTICAL_0_10_.UN1\ : std_logic ;
  signal \COUNTFORVERTICAL_0_10_.UN0\ : std_logic ;
  signal \VGAR_0_0_.UN3\ : std_logic ;
  signal \VGAR_0_0_.UN1\ : std_logic ;
  signal \VGAR_0_0_.UN0\ : std_logic ;
  signal \VGAR_0_1_.UN3\ : std_logic ;
  signal \VGAR_0_1_.UN1\ : std_logic ;
  signal \VGAR_0_1_.UN0\ : std_logic ;
  signal \VGAG_0_0_.UN3\ : std_logic ;
  signal \VGAG_0_0_.UN1\ : std_logic ;
  signal \VGAG_0_0_.UN0\ : std_logic ;
  signal \VGAG_0_1_.UN3\ : std_logic ;
  signal \VGAG_0_1_.UN1\ : std_logic ;
  signal \VGAG_0_1_.UN0\ : std_logic ;
  signal \VGAB_0_0_.UN3\ : std_logic ;
  signal \VGAB_0_0_.UN1\ : std_logic ;
  signal \VGAB_0_0_.UN0\ : std_logic ;
  signal \VGAB_0_1_.UN3\ : std_logic ;
  signal \VGAB_0_1_.UN1\ : std_logic ;
  signal \VGAB_0_1_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_4_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_4_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_4_.UN0\ : std_logic ;
  signal \COUNTFORCOLOR_0_0_.UN3\ : std_logic ;
  signal \COUNTFORCOLOR_0_0_.UN1\ : std_logic ;
  signal \COUNTFORCOLOR_0_0_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_6_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_6_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_6_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_5_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_5_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_5_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_3_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_3_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_3_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_1_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_1_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_3_1_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_9_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_9_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_9_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_8_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_8_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_8_.UN0\ : std_logic ;
  signal \COUNTFORPH_0_6_.UN3\ : std_logic ;
  signal \COUNTFORPH_0_6_.UN1\ : std_logic ;
  signal \COUNTFORPH_0_6_.UN0\ : std_logic ;
  signal \COUNTFORPH_0_5_.UN3\ : std_logic ;
  signal \COUNTFORPH_0_5_.UN1\ : std_logic ;
  signal \COUNTFORPH_0_5_.UN0\ : std_logic ;
  signal \COUNTFORPH_0_4_.UN3\ : std_logic ;
  signal \COUNTFORPH_0_4_.UN1\ : std_logic ;
  signal \COUNTFORPH_0_4_.UN0\ : std_logic ;
  signal \COUNTFORPH_0_2_.UN3\ : std_logic ;
  signal \COUNTFORPH_0_2_.UN1\ : std_logic ;
  signal \COUNTFORPH_0_2_.UN0\ : std_logic ;
  signal \COUNTFORPH_0_1_.UN3\ : std_logic ;
  signal \COUNTFORPH_0_1_.UN1\ : std_logic ;
  signal \COUNTFORPH_0_1_.UN0\ : std_logic ;
  signal \COUNTFORPH_0_0_.UN3\ : std_logic ;
  signal \COUNTFORPH_0_0_.UN1\ : std_logic ;
  signal \COUNTFORPH_0_0_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_2_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_2_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_2_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_6_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_6_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_6_.UN0\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_7_.UN3\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_7_.UN1\ : std_logic ;
  signal \COUNTFORHORIZONTAL_0_7_.UN0\ : std_logic ;
  signal VCC : std_logic ;
  component DFF
    port(
      Q : out std_logic;
      D : in std_logic;
      CLK : in std_logic  );
  end component;
  component IBUF
    port(
      O : out std_logic;
      I0 : in std_logic  );
  end component;
  component OBUF
    port(
      O : out std_logic;
      I0 : in std_logic  );
  end component;
  component AND2
    port(
      O : out std_logic;
      I0 : in std_logic;
      I1 : in std_logic  );
  end component;
  component INV
    port(
      O : out std_logic;
      I0 : in std_logic  );
  end component;
  component OR2
    port(
      O : out std_logic;
      I0 : in std_logic;
      I1 : in std_logic  );
  end component;
  component XOR2
    port(
      O : out std_logic;
      I0 : in std_logic;
      I1 : in std_logic  );
  end component;
begin
  GND <= '0';
  \II_countforph_cZ[0]\: DFF port map (
      Q => COUNTFORPH(0),
      D => N_42,
      CLK => CLK_I_0);
  \II_countforph_cZ[1]\: DFF port map (
      Q => COUNTFORPH(1),
      D => N_43,
      CLK => CLK_I_0);
  \II_countforph_cZ[2]\: DFF port map (
      Q => COUNTFORPH(2),
      D => N_44,
      CLK => CLK_I_0);
  \II_countforph_cZ[3]\: DFF port map (
      Q => COUNTFORPH(3),
      D => N_45,
      CLK => CLK_I_0);
  \II_countforph_cZ[4]\: DFF port map (
      Q => COUNTFORPH(4),
      D => N_46,
      CLK => CLK_I_0);
  \II_countforph_cZ[5]\: DFF port map (
      Q => COUNTFORPH(5),
      D => N_47,
      CLK => CLK_I_0);
  \II_countforph_cZ[6]\: DFF port map (
      Q => COUNTFORPH(6),
      D => N_48,
      CLK => CLK_I_0);
  \II_countforcolor_cZ[0]\: DFF port map (
      Q => COUNTFORCOLOR(0),
      D => N_36,
      CLK => CLK_I_0);
  \II_countforcolor_cZ[1]\: DFF port map (
      Q => COUNTFORCOLOR(1),