videogenerator.vhm

用lattice XP3 demo板设计的VGA信号发生器

--
-- Written by Synplicity
-- Mon Jun 18 08:11:34 2007
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity MACH_DFF is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CLK :  in std_logic;
  R :  in std_logic;
  S :  in std_logic;
  NOTIFIER :  in std_logic);
end MACH_DFF;

architecture beh of MACH_DFF is
  signal UN0 : std_logic ;
  signal UN1 : std_logic ;
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  UN0 <= not S;
  UN1 <= not R;
  VCC <= '1';
  GND <= '0';
  II_Q_Z: prim_dff port map (Q, D, CLK, UN1, UN0);
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity AND2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end AND2;

architecture beh of AND2 is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  VCC <= '1';
  GND <= '0';
  O <= I0 and I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity DFF is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CLK :  in std_logic);
end DFF;

architecture beh of DFF is
  signal VCC : std_logic ;
  signal GND : std_logic ;
  component MACH_DFF
    port(
      Q : out std_logic;
      D : in std_logic;
      CLK : in std_logic;
      R : in std_logic;
      S : in std_logic;
      NOTIFIER : in std_logic  );
  end component;
begin
  II_INS4: MACH_DFF port map (
      Q => Q,
      D => D,
      CLK => CLK,
      R => VCC,
      S => VCC,
      NOTIFIER => GND);
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity IBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end IBUF;

architecture beh of IBUF is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  O <= I0;
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity INV is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end INV;

architecture beh of INV is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  O <= not I0;
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity OBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end OBUF;

architecture beh of OBUF is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  O <= I0;
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity OR2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end OR2;

architecture beh of OR2 is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  VCC <= '1';
  GND <= '0';
  O <= I0 or I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity XOR2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end XOR2;

architecture beh of XOR2 is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  VCC <= '1';
  GND <= '0';
  O <= I0 xor I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity VideoGenerator is
port(
  clk :  in std_logic;
  UARTrx :  in std_logic;
  UARTtx :  out std_logic;
  VGAr : out std_logic_vector (1 downto 0);
  VGAg : out std_logic_vector (1 downto 0);
  VGAb : out std_logic_vector (1 downto 0);
  VGAh_cs :  out std_logic;
  VGAv :  out std_logic;
  VGAdena :  out std_logic;
  NUMlocation : out std_logic_vector (3 downto 0);
  NUMdata : out std_logic_vector (7 downto 0);
  key :  in std_logic);
end VideoGenerator;

architecture beh of VideoGenerator is
  signal COUNTFORHORIZONTAL : std_logic_vector (12 downto 0);
  signal UN1_COUNTFORPH : std_logic_vector (6 downto 1);
  signal COUNTFORPH : std_logic_vector (6 downto 0);
  signal COUNTFORVERTICAL : std_logic_vector (12 downto 0);
  signal COUNTFORCOLOR : std_logic_vector (5 downto 0);
  signal COUNTFORPH_4 : std_logic_vector (6 downto 0);
  signal UN2_COUNTFORHORIZONTAL_1 : std_logic_vector (12 downto 1);
  signal COUNTFORHORIZONTAL_3 : std_logic_vector (10 downto 0);
  signal COUNTFORVERTICAL_3 : std_logic_vector (12 downto 0);
  signal VGAR_5 : std_logic_vector (1 downto 0);
  signal VGAG_4 : std_logic_vector (1 downto 0);
  signal VGAB_4 : std_logic_vector (1 downto 0);
  signal COUNTFORCOLOR_2 : std_logic_vector (5 downto 0);
  signal UN1_COUNTFORVERTICAL : std_logic_vector (12 downto 1);
  signal COUNTFORVERTICAL_3_I_0 : std_logic_vector (12 downto 3);
  signal COUNTFORVERTICAL_I_0 : std_logic_vector (2 downto 0);
  signal UN1_COUNTFORVERTICAL_I_0 : std_logic_vector (12 downto 1);
  signal UN2_COUNTFORHORIZONTAL_1_I_0 : std_logic_vector (12 downto 2);
  signal COUNTFORHORIZONTAL_3_I_0 : std_logic_vector (10 downto 3);
  signal COUNTFORHORIZONTAL_I_0 : std_logic_vector (0 to 0);
  signal COUNTFORPH_I_0 : std_logic_vector (6 downto 0);
  signal UN1_COUNTFORPH_I_0 : std_logic_vector (6 downto 4);
  signal VGAR_C : std_logic_vector (1 downto 0);
  signal VGAG_C : std_logic_vector (1 downto 0);
  signal VGAB_C : std_logic_vector (1 downto 0);
  signal UN1_COUNTFORVERTICAL_I : std_logic_vector (11 downto 2);
  signal COUNTFORVERTICAL_3_I : std_logic_vector (5 downto 2);
  signal COUNTFORHORIZONTAL_3_I : std_logic_vector (1 downto 0);
  signal UN2_COUNTFORHORIZONTAL_1_I : std_logic_vector (10 to 10);
  signal PIXELCLOCK : std_logic ;
  signal N_2 : std_logic ;
  signal N_3 : std_logic ;
  signal N_4 : std_logic ;
  signal N_5 : std_logic ;
  signal N_6 : std_logic ;
  signal N_7 : std_logic ;
  signal N_8 : std_logic ;
  signal N_9 : std_logic ;
  signal N_10 : std_logic ;
  signal N_11 : std_logic ;
  signal N_12 : std_logic ;
  signal N_13 : std_logic ;
  signal N_14 : std_logic ;
  signal N_15 : std_logic ;
  signal N_16 : std_logic ;
  signal N_17 : std_logic ;
  signal N_18 : std_logic ;
  signal N_19 : std_logic ;
  signal N_20 : std_logic ;
  signal N_21 : std_logic ;
  signal N_22 : std_logic ;
  signal N_23 : std_logic ;
  signal N_24 : std_logic ;
  signal N_25 : std_logic ;
  signal N_26 : std_logic ;
  signal N_27 : std_logic ;
  signal N_28 : std_logic ;
  signal N_29 : std_logic ;
  signal N_30 : std_logic ;
  signal N_31 : std_logic ;
  signal N_32 : std_logic ;
  signal N_33 : std_logic ;
  signal N_34 : std_logic ;
  signal N_35 : std_logic ;
  signal N_36 : std_logic ;
  signal N_37 : std_logic ;
  signal N_38 : std_logic ;
  signal N_39 : std_logic ;
  signal N_40 : std_logic ;
  signal N_41 : std_logic ;
  signal N_42 : std_logic ;
  signal N_43 : std_logic ;
  signal N_44 : std_logic ;
  signal N_45 : std_logic ;
  signal N_46 : std_logic ;
  signal N_47 : std_logic ;
  signal N_48 : std_logic ;
  signal N_49 : std_logic ;
  signal GND : std_logic ;
  signal N_556 : std_logic ;
  signal N_384 : std_logic ;
  signal N_381 : std_logic ;
  signal N_400 : std_logic ;
  signal UN77_PIXELCLOCK : std_logic ;
  signal N_397 : std_logic ;
  signal N_409 : std_logic ;
  signal N_406 : std_logic ;
  signal N_403 : std_logic ;
  signal N_419 : std_logic ;
  signal N_422 : std_logic ;
  signal N_434 : std_logic ;
  signal N_431 : std_logic ;
  signal N_437 : std_logic ;
  signal UN7_PIXELCLOCK : std_logic ;
  signal UN7_PIXELCLOCK_3 : std_logic ;
  signal N_289 : std_logic ;
  signal N_530 : std_logic ;
  signal N_446 : std_logic ;
  signal N_443 : std_logic ;
  signal N_440 : std_logic ;
  signal N_231 : std_logic ;
  signal UN25_PIXELCLOCK : std_logic ;
  signal UN33_PIXELCLOCK : std_logic ;
  signal UN29_PIXELCLOCK : std_logic ;
  signal VGAV_2_SQMUXA : std_logic ;
  signal UN11_PIXELCLOCK : std_logic ;
  signal N_309 : std_logic ;
  signal VGAV_2 : std_logic ;
  signal VGAV_2_F1 : std_logic ;
  signal VGAV_1_SQMUXA : std_logic ;
  signal VGAH_CS_I_M : std_logic ;
  signal N_374 : std_logic ;
  signal N_378 : std_logic ;
  signal N_387 : std_logic ;
  signal N_425 : std_logic ;
  signal N_428 : std_logic ;
  signal N_480 : std_logic ;
  signal N_483 : std_logic ;
  signal N_486 : std_logic ;
  signal N_135 : std_logic ;
  signal N_130 : std_logic ;
  signal N_139 : std_logic ;
  signal N_136 : std_logic ;
  signal N_547 : std_logic ;
  signal N_241 : std_logic ;
  signal N_238 : std_logic ;
  signal VGADENA_0_SQMUXA : std_logic ;
  signal UN65_PIXELCLOCK : std_logic ;
  signal UN63_PIXELCLOCK : std_logic ;
  signal UN51_PIXELCLOCK_1 : std_logic ;
  signal VGADENA_0_SQMUXA_1 : std_logic ;
  signal N_1 : std_logic ;
  signal N_449 : std_logic ;
  signal N_459 : std_logic ;
  signal N_462 : std_logic ;
  signal N_489 : std_logic ;
  signal N_477 : std_logic ;
  signal N_474 : std_logic ;
  signal N_348 : std_logic ;
  signal N_129_1 : std_logic ;
  signal N_249 : std_logic ;
  signal N_125 : std_logic ;
  signal N_129 : std_logic ;
  signal N_252 : std_logic ;
  signal N_468 : std_logic ;
  signal N_465 : std_logic ;
  signal COUNTFORVERTICAL_3_SN_N_2 : std_logic ;
  signal N_255 : std_logic ;
  signal N_253 : std_logic ;
  signal N_250 : std_logic ;
  signal N_471 : std_logic ;
  signal N_428_I : std_logic ;
  signal UN25_PIXELCLOCK_I_0 : std_logic ;
  signal N_249_I_0 : std_logic ;