videogenerator.lco

用lattice XP3 demo板设计的VGA信号发生器

[DEVICE]
Family = lc4k;
PartType = LA4128V;
Package = 100TQFP;
PartNumber = LA4128V-75TN100E;
Speed = -7.5;
Operating_condition = AUTO;
EN_Segment = Yes;
Pin_MC_1to1 = No;
Default_Device_Io_Types=LVCMOS18,-;
Voltage = 3.3;

[REVISION]
RCS = "$Header $";
Parent = lc4k128v.lci;
Design = ;
DATE = 06/18/2007;
TIME = 08:47:02;
Source_Format = Schematic_VHDL;
Type = ;
Pre_Fit_Time = ;

[IGNORE ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;
IO_Types = No;

[CLEAR ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;
IO_Types = No;

[BACKANNOTATE ASSIGNMENTS]
Pin_Assignment = No;
Pin_Block = No;
Pin_Macrocell_Block = No;
Routing = No;
Io_Types = No;

[GLOBAL CONSTRAINTS]
Max_Fanin = 24;
Max_PTerm_Split = 80;
Max_PTerm_Collapse = 16;
Max_Pin_Percent = 100;
Max_Macrocell_Percent = 100;
Max_GLB_Input_Percent = 100;
Logic_Reduction = Yes;
XOR_Synthesis = Yes;
Keep_XOR = No;
DT_Synthesis = Yes;
Node_Collapse = Yes;
Nodes_collapsing_mode = FMAX;
Fmax_Logic_Level = 1;
Use_CE = Yes;
Use_Internal_COM_FB = Yes;
Set_Reset_Swap = No;
Clock_Optimize = No;
EN_Set_Reset_Dont_Care = No;
TOE_AS_IO = No;
Set_Reset_Dont_Care = No;
EN_In_Reg_Optimize = No;
In_Reg_Optimize = Yes;
Run_Time = 0;
Routing_Attempts = 2;
Balanced_Partitioning = Yes;
Spread_Placement = Yes;
Usercode = ;
Usercode_Format = HEX;
Vcc = ;
Dual_Function_Macrocell = 1;
Global_PTOE = Yes;
Hard_Fast_Bypass = No;
Fitter_Effort_Level = LOW;
Auto_buffering_for_high_glb_fanin = Off;
Auto_buffering_for_low_bonded_io = Off;
User_max_glb_fanin = 36;
Adjust_input_assignments = Off;

[LOCATION ASSIGNMENTS]
// Block A
NUMdata_4_=pin,91,-,A,0;
VGAr_1_=pin,92,-,A,3;
inst_pixelClock=node,-,-,A,4;
countforvertical_0_=node,-,-,A,2;
countforvertical_4_=node,-,-,A,10;
countforvertical_5_=node,-,-,A,5;
countforvertical_8_=node,-,-,A,6;
countforcolor_5_=node,-,-,A,7;
N_639=node,-,-,A,1;
un29_pixelclock=node,-,-,A,12;
G_397=node,-,-,A,8;
N_252=node,-,-,A,9;
// Block B
NUMdata_3_=pin,3,-,B,0;
UARTtx=pin,9,-,B,1;
NUMlocation_0_=pin,4,-,B,2;
VGAdena=pin,10,-,B,3;
VGAr_0_=pin,5,-,B,4;
countforvertical_6_=node,-,-,B,12;
countforvertical_9_=node,-,-,B,7;
countforvertical_10_=node,-,-,B,5;
countforvertical_11_=node,-,-,B,9;
countforvertical_12_=node,-,-,B,8;
countforcolor_4_=node,-,-,B,6;
// Block C
NUMdata_2_=pin,16,-,C,0;
NUMdata_6_=pin,15,-,C,1;
VGAv=pin,22,-,C,7;
N_428=node,-,-,C,9;
countforvertical_3_6__n=node,-,-,C,4;
countforvertical_3_3__n=node,-,-,C,5;
N_474=node,-,-,C,12;
// Block D
NUMlocation_3_=pin,37,-,D,0;
countforvertical_1_=node,-,-,D,3;
countforvertical_2_=node,-,-,D,5;
countforvertical_3_=node,-,-,D,12;
countforvertical_7_=node,-,-,D,4;
un63_pixelclock_i_0=node,-,-,D,1;
G_391=node,-,-,D,6;
N_483=node,-,-,D,2;
G_389=node,-,-,D,7;
countforvertical_3_4__n=node,-,-,D,9;
// Block E
NUMdata_1_=pin,41,-,E,0;
NUMdata_7_=pin,48,-,E,1;
NUMlocation_2_=pin,42,-,E,2;
NUMlocation_1_=pin,49,-,E,3;
VGAh_cs=pin,43,-,E,5;
countforhorizontal_0_=node,-,-,E,10;
countforhorizontal_2_=node,-,-,E,7;
countforhorizontal_3_=node,-,-,E,12;
countforhorizontal_6_=node,-,-,E,6;
countforhorizontal_10_=node,-,-,E,8;
un51_pixelclock_1_i_0=node,-,-,E,4;
un7_pixelclock=node,-,-,E,9;
// Block F
NUMdata_0_=pin,53,-,F,0;
NUMdata_5_=pin,59,-,F,1;
countforph_0_=node,-,-,F,12;
countforph_5_=node,-,-,F,4;
countforhorizontal_4_=node,-,-,F,5;
countforhorizontal_11_=node,-,-,F,3;
countforhorizontal_12_=node,-,-,F,7;
N_636=node,-,-,F,2;
G_342=node,-,-,F,9;
// Block G
VGAg_1_=pin,72,-,G,5;
VGAb_0_=pin,66,-,G,0;
countforph_1_=node,-,-,G,6;
countforph_2_=node,-,-,G,1;
countforph_3_=node,-,-,G,4;
countforph_4_=node,-,-,G,8;
countforph_6_=node,-,-,G,2;
countforcolor_0_=node,-,-,G,3;
countforcolor_3_=node,-,-,G,7;
N_556=node,-,-,G,9;
N_406=node,-,-,G,10;
N_374=node,-,-,G,12;
// Block H
VGAb_1_=pin,86,-,H,6;
VGAg_0_=pin,87,-,H,2;
countforhorizontal_1_=node,-,-,H,3;
countforhorizontal_5_=node,-,-,H,4;
countforhorizontal_7_=node,-,-,H,8;
countforhorizontal_8_=node,-,-,H,10;
countforhorizontal_9_=node,-,-,H,11;
countforcolor_1_=node,-,-,H,7;
countforcolor_2_=node,-,-,H,5;
N_542_i_0=node,-,-,H,1;
N_381=node,-,-,H,12;
N_530=node,-,-,H,0;
N_443=node,-,-,H,13;
un25_pixelclock=node,-,-,H,9;
// Input/Clock Pins
clk=pin,89,-,-,-;

[PTOE ASSIGNMENTS]

[FAST BYPASS]
Default=NONE;
BYPASS=;

[ORP BYPASS]
default=NONE;

[INPUT REGISTERS]
Default=NONE;
;

[IO TYPES]
clk=LVCMOS18,pin,-,-;
NUMdata_4_=LVCMOS18,pin,0,-;
NUMdata_3_=LVCMOS18,pin,0,-;
NUMdata_2_=LVCMOS18,pin,0,-;
NUMdata_1_=LVCMOS18,pin,1,-;
NUMdata_0_=LVCMOS18,pin,1,-;
NUMlocation_3_=LVCMOS18,pin,0,-;
NUMdata_7_=LVCMOS18,pin,1,-;
UARTtx=LVCMOS18,pin,0,-;
NUMlocation_2_=LVCMOS18,pin,1,-;
NUMlocation_1_=LVCMOS18,pin,1,-;
NUMlocation_0_=LVCMOS18,pin,0,-;
NUMdata_6_=LVCMOS18,pin,0,-;
NUMdata_5_=LVCMOS18,pin,1,-;
VGAr_1_=LVCMOS18,pin,0,-;
VGAg_1_=LVCMOS18,pin,1,-;
VGAb_1_=LVCMOS18,pin,1,-;
VGAh_cs=LVCMOS18,pin,1,-;
VGAv=LVCMOS18,pin,0,-;
VGAdena=LVCMOS18,pin,0,-;
VGAr_0_=LVCMOS18,pin,0,-;
VGAg_0_=LVCMOS18,pin,1,-;
VGAb_0_=LVCMOS18,pin,1,-;

[PLL ASSIGNMENTS]

[RESOURCE RESERVATIONS]
Layer=Off;

[SLEWRATE]
Default=FAST;

[PULLUP]
Default=UP;

[FITTER RESULTS]
I/O_pin_util = 31;
I/O_pin = 20;
Logic_PT_util = 44;
Logic_PT = 284;
Occupied_MC_util = 75;
Occupied_MC = 96;
Occupied_PT_util = 66;
Occupied_PT = 442;
GLB_input_util = 61;
GLB_input = 176;

[TIMING CONSTRAINTS]

[FITTER REPORT FORMAT]
Fitter_Options = Yes;
Pinout_Diagram = No;
Pinout_Listing = Yes;
Detailed_Block_Segment_Summary = Yes;
Input_Signal_List = Yes;
Output_Signal_List = Yes;
Bidir_Signal_List = Yes;
Node_Signal_List = Yes;
Signal_Fanout_List = Yes;
Block_Segment_Fanin_List = Yes;
Postfit_Eqn = Yes;
Page_Break = Yes;
Detailed = No;

[POWER]
Default=HIGH;

[SOURCE_CONSTRAINT_OPTION]

[HARDWARE DEVICE OPTIONS]
Zero_Hold_Time = No;
Signature_Word = ;
Pullup = No;
Slew_Rate = FAST;

[TIMING ANALYZER]
Last_source=;
Last_source_type=Fmax;