📄 videogenerator.rpt
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|--------------------------------------------------------------|
|- ispLEVER 6.1.00.37.42.06 Fitter Report File -|
|- Copyright(C), 1992-2005, Lattice Semiconductor Corporation -|
|- All Rights Reserved. -|
|--------------------------------------------------------------|
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Project_Summary
~~~~~~~~~~~~~~~
Project Name : videogenerator
Project Path : D:\FPGA\VideoGenerator
Project Fitted on : Mon Jun 18 08:47:09 2007
Device : M4128_64
Package : 100
GLB Input Mux Size : 19
Available Blocks : 8
Speed : -7.5
Part Number : LA4128V-75TN100E
Source Format : Schematic_VHDL
// Project 'videogenerator' Fit Successfully! //
Compilation_Times
~~~~~~~~~~~~~~~~~
Prefit Time 0 secs
Load Design Time 0.13 secs
Partition Time 0.20 secs
Place Time 0.02 secs
Route Time 0.00 secs
Total Fit Time 00:00:01
Design_Summary
~~~~~~~~~~~~~~
Total Input Pins 1
Total Logic Functions 87
Total Output Pins 22
Total Bidir I/O Pins 0
Total Buried Nodes 65
Total Flip-Flops 49
Total D Flip-Flops 45
Total T Flip-Flops 4
Total Latches 0
Total Product Terms 333
Total Reserved Pins 0
Total Locked Pins 0
Total Locked Nodes 0
Total Unique Output Enables 0
Total Unique Clocks 1
Total Unique Clock Enables 0
Total Unique Resets 0
Total Unique Presets 0
Fmax Logic Levels 4
Device_Resource_Summary
~~~~~~~~~~~~~~~~~~~~~~~
Device
Total Used Not Used Utilization
-----------------------------------------------------------------------
Dedicated Pins
Clock/Input Pins 4 1 3 --> 25
Input-Only Pins 6 0 6 --> 0
I/O / Enable Pins 2 2 0 --> 100
I/O Pins 62 20 42 --> 32
Logic Functions 128 87 41 --> 67
Input Registers 64 0 64 --> 0
GLB Inputs 288 176 112 --> 61
Logical Product Terms 640 284 356 --> 44
Occupied GLBs 8 8 0 --> 100
Macrocells 128 87 41 --> 67
Control Product Terms:
GLB Clock/Clock Enables 8 0 8 --> 0
GLB Reset/Presets 8 0 8 --> 0
Macrocell Clocks 128 0 128 --> 0
Macrocell Clock Enables 128 0 128 --> 0
Macrocell Enables 128 0 128 --> 0
Macrocell Resets 128 0 128 --> 0
Macrocell Presets 128 0 128 --> 0
Global Routing Pool 220 74 146 --> 33
GRP from IFB .. 0 .. --> ..
(from input signals) .. 0 .. --> ..
(from output signals) .. 0 .. --> ..
(from bidir signals) .. 0 .. --> ..
GRP from MFB .. 74 .. --> ..
----------------------------------------------------------------------
<Note> 1 : The available PT is the product term that has not been used.
<Note> 2 : IFB is I/O feedback.
<Note> 3 : MFB is macrocell feedback.
GLB_Resource_Summary
~~~~~~~~~~~~~~~~~~~~
# of PT
--- Fanin --- I/O Input Macrocells Macrocells Logic clusters
Unique Shared Total Pins Regs Used Inaccessible available PTs used
-------------------------------------------------------------------------------------------
Maximum
GLB 36 *(1) 8 -- -- 16 80 16
-------------------------------------------------------------------------------------------
GLB A 5 23 28 1/8 0 12 0 4 32 12
GLB B 10 13 23 5/8 0 11 0 5 28 12
GLB C 11 21 32 3/8 0 7 3 6 48 11
GLB D 4 15 19 1/8 0 10 0 6 32 11
-------------------------------------------------------------------------------------------
GLB E 1 14 15 5/8 0 12 0 4 40 13
GLB F 8 12 20 2/8 0 9 0 7 31 11
GLB G 3 13 16 2/8 0 12 0 4 34 12
GLB H 2 21 23 1/8 0 14 0 2 39 14
-------------------------------------------------------------------------------------------
TOTALS: 44 132 176 20/64 0 87 3 38 284 96
<Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB.
<Note> 2 : Four rightmost columns above reflect last status of the placement process.
GLB_Control_Summary
~~~~~~~~~~~~~~~~~~~
Shared Shared | Mcell Mcell Mcell Mcell Mcell
Clk/CE Rst/Pr | Clock CE Enable Reset Preset
------------------------------------------------------------------------------
Maximum
GLB 1 1 16 16 16 16 16
==============================================================================
GLB A 0 0 0 0 0 0 0
GLB B 0 0 0 0 0 0 0
GLB C 0 0 0 0 0 0 0
GLB D 0 0 0 0 0 0 0
------------------------------------------------------------------------------
GLB E 0 0 0 0 0 0 0
GLB F 0 0 0 0 0 0 0
GLB G 0 0 0 0 0 0 0
GLB H 0 0 0 0 0 0 0
------------------------------------------------------------------------------
<Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB.
Optimizer_and_Fitter_Options
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Pin Assignment : No
Group Assignment : No
Pin Reservation : No
@Ignore_Project_Constraints :
Pin Assignments : No
Keep Block Assignment --
Keep Segment Assignment --
Group Assignments : No
Macrocell Assignment : No
Keep Block Assignment --
Keep Segment Assignment --
@Backannotate_Project_Constraints
Pin Assignments : No
Pin And Block Assignments : No
Pin, Macrocell and Block : No
@Timing_Constraints : No
@Global_Project_Optimization :
Balanced Partitioning : Yes
Spread Placement : Yes
Note :
Pack Design :
Balanced Partitioning = No
Spread Placement = No
Spread Design :
Balanced Partitioning = Yes
Spread Placement = Yes
@Logic_Synthesis :
Logic Reduction : Yes
Node Collapsing : FMAX
Fmax_Logic_Level : 1
D/T Synthesis : Yes
XOR Synthesis : Yes
Max. P-Term for Collapsing : 16
Max. P-Term for Splitting : 80
Max Symbols : 24
@Utilization_options
Max. % of Macrocells used : 100
@Usercode (HEX)
@IO_Types Default = LVCMOS18 (2)
@Output_Slew_Rate Default = FAST (2)
@Power Default = HIGH (2)
@Pull Default = PULLUP_UP (2)
@Fast_Bypass Default = None (2)
@ORP_Bypass Default = None
@Input_Registers Default = None (2)
@Register_Powerup Default = None
Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
Bidir and Buried Signal Lists.
Pinout_Listing
~~~~~~~~~~~~~~
| Pin | Bank |GLB |Assigned| | Signal|
Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name
--------------------------------------------------------------------------------------
1 | GND | - | | | | |
2 | TDI | - | | | | |
3 | I_O | 0 |B0 | |LVCMOS18 | Output|NUMdata_3_
4 | I_O | 0 |B2 | |LVCMOS18 | Output|NUMlocation_0_
5 | I_O | 0 |B4 | |LVCMOS18 | Output|VGAr_0_
6 | I_O | 0 |B6 | | | |
7 |GNDIO0 | - | | | | |
8 | I_O | 0 |B8 | | | |
9 | I_O | 0 |B10 | |LVCMOS18 | Output|UARTtx
10 | I_O | 0 |B12 | |LVCMOS18 | Output|VGAdena
11 | I_O | 0 |B13 | | | |
12 | IN0 | 0 | | | | |
13 |VCCIO0 | - | | | | |
14 | I_O | 0 |C14 | | | |
15 | I_O | 0 |C12 | |LVCMOS18 | Output|NUMdata_6_
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