videogenerator.tlg

用lattice XP3 demo板设计的VGA信号发生器

@N: CD630 :"D:\fpga\VIDEOG~1\videogenerator.vhd":5:7:5:20|Synthesizing work.videogenerator.videogeneratorarchitecture 
@W: CD638 :"D:\fpga\VIDEOG~1\videogenerator.vhd":56:7:56:13|Signal number1 is undriven 
@W: CD638 :"D:\fpga\VIDEOG~1\videogenerator.vhd":57:7:57:13|Signal number2 is undriven 
@W: CD638 :"D:\fpga\VIDEOG~1\videogenerator.vhd":58:7:58:13|Signal number3 is undriven 
@W: CD638 :"D:\fpga\VIDEOG~1\videogenerator.vhd":59:7:59:13|Signal number4 is undriven 
@W: CD638 :"D:\fpga\VIDEOG~1\videogenerator.vhd":60:7:60:11|Signal clock is undriven 
Post processing for work.videogenerator.videogeneratorarchitecture
@W: CL163 :"D:\fpga\VIDEOG~1\videogenerator.vhd":57:7:57:13|Bit <0> of signal number2 is floating
@W: CL163 :"D:\fpga\VIDEOG~1\videogenerator.vhd":57:7:57:13|Bit <1> of signal number2 is floating
@W: CL163 :"D:\fpga\VIDEOG~1\videogenerator.vhd":57:7:57:13|Bit <2> of signal number2 is floating
@W: CL163 :"D:\fpga\VIDEOG~1\videogenerator.vhd":57:7:57:13|Bit <3> of signal number2 is floating
@W: CL163 :"D:\fpga\VIDEOG~1\videogenerator.vhd":57:7:57:13|Bit <4> of signal number2 is floating
@W: CL163 :"D:\fpga\VIDEOG~1\videogenerator.vhd":57:7:57:13|Bit <5> of signal number2 is floating
@W: CL163 :"D:\fpga\VIDEOG~1\videogenerator.vhd":57:7:57:13|Bit <6> of signal number2 is floating
@W: CL163 :"D:\fpga\VIDEOG~1\videogenerator.vhd":57:7:57:13|Bit <7> of signal number2 is floating
@W: CL162 :"D:\fpga\VIDEOG~1\videogenerator.vhd":18:1:18:7|NUMdata is not assigned a value (floating) 
@W: CL162 :"D:\fpga\VIDEOG~1\videogenerator.vhd":17:1:17:11|NUMlocation is not assigned a value (floating) 
@W: CL162 :"D:\fpga\VIDEOG~1\videogenerator.vhd":10:1:10:6|UARTtx is not assigned a value (floating) 
@W: CL159 :"D:\fpga\VIDEOG~1\videogenerator.vhd":9:1:9:6|Input UARTrx is unused
@W: CL159 :"D:\fpga\VIDEOG~1\videogenerator.vhd":19:1:19:3|Input key is unused