videogenerator.tw1

用lattice XP3 demo板设计的VGA信号发生器

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Lattice TRACE Report, Version ispLever_v61_PROD_Build (37)
Sat Jun 16 17:34:46 2007

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2006 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -gt -o checkpnt.twr videogenerator_map.ncd videogenerator.prf 
Design file:     videogenerator_map.ncd
Preference file: videogenerator.prf
Device,speed:    LFXP3C,3
Report level:    verbose report, limited to 1 item per preference
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BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY PORT "clk" 86.866000 MHz ;
            0 items scored, 0 timing errors detected.
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Passed:  The following path meets requirements by 9.593ns
         The internal maximum frequency of the following component is 521.376 MHz

 Logical Details:  Cell type  Pin type       Component name

   Source:         FSLICE     Clock          SLICE_14
   Destination:    FSLICE     Data in        SLICE_14

   Delay:               1.918ns -- based on Minimum Pulse Width

Report:  521.376MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY NET "clk_c" 86.866000 MHz ;
            4096 items scored, 0 timing errors detected.
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Passed:  The following path meets requirements by 4.834ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              countforhorizontal_fast_0  (from clk_c -)
   Destination:    FF         Data in        VGAdenaZ0  (to clk_c -)

   Delay:               6.498ns  (100.0% logic, 0.0% route), 15 logic levels.

 Constraint Details:

       6.498ns physical path delay SLICE_28 to SLICE_14 meets
      11.511ns delay constraint less
       0.179ns DIN_SET requirement (totaling 11.332ns) by 4.834ns

 Physical Path Details:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.631   SLICE_28.CLK to    SLICE_28.Q0 SLICE_28 (from clk_c)
ROUTE         2   e 0.000    SLICE_28.Q0 to     SLICE_0.A0 countforhorizontal_fastZ0Z_0
A0TOFCO_DE  ---     0.907     SLICE_0.A0 to    SLICE_0.FCO SLICE_0
ROUTE         1   e 0.000    SLICE_0.FCO to   SLICE_13.FCI un2_countforhorizontal_1_0_cry_1
FCITOFCO_D  ---     0.145   SLICE_13.FCI to   SLICE_13.FCO SLICE_13
ROUTE         1   e 0.000   SLICE_13.FCO to   SLICE_12.FCI un2_countforhorizontal_1_0_cry_3
FCITOFCO_D  ---     0.145   SLICE_12.FCI to   SLICE_12.FCO SLICE_12
ROUTE         1   e 0.000   SLICE_12.FCO to   SLICE_11.FCI un2_countforhorizontal_1_0_cry_5
FCITOFCO_D  ---     0.145   SLICE_11.FCI to   SLICE_11.FCO SLICE_11
ROUTE         1   e 0.000   SLICE_11.FCO to   SLICE_10.FCI un2_countforhorizontal_1_0_cry_7
FCITOFCO_D  ---     0.145   SLICE_10.FCI to   SLICE_10.FCO SLICE_10
ROUTE         1   e 0.000   SLICE_10.FCO to    SLICE_9.FCI un2_countforhorizontal_1_0_cry_9
TLATCH_DEL  ---     1.324    SLICE_9.FCI to     SLICE_9.Q1 SLICE_9
ROUTE         5   e 0.000     SLICE_9.Q1 to    SLICE_77.D0 un2_countforhorizontal_1_n_11
CTOF_DEL    ---     0.382    SLICE_77.D0 to    SLICE_77.F0 SLICE_77
ROUTE         2   e 0.000    SLICE_77.F0 to    SLICE_48.D1 un25_pixelclock_7_m2_0_a2_a0_x_sx
CTOF_DEL    ---     0.382    SLICE_48.D1 to    SLICE_48.F1 SLICE_48
ROUTE         1   e 0.000    SLICE_48.F1 to    SLICE_55.B1 un25_pixelclock_7_m2_0_a2_a0_xZ0
CTOF_DEL    ---     0.382    SLICE_55.B1 to    SLICE_55.F1 SLICE_55
ROUTE         1   e 0.000    SLICE_55.F1 to    SLICE_58.C1 un25_pixelclockZ0Z_1
CTOF_DEL    ---     0.382    SLICE_58.C1 to    SLICE_58.F1 SLICE_58
ROUTE        15   e 0.000    SLICE_58.F1 to    SLICE_66.D1 un25_pixelclockZ0
CTOF_DEL    ---     0.382    SLICE_66.D1 to    SLICE_66.F1 SLICE_66
ROUTE         2   e 0.000    SLICE_66.F1 to    SLICE_75.D0 un69_pixelclocklto6_0
CTOF_DEL    ---     0.382    SLICE_75.D0 to    SLICE_75.F0 SLICE_75
ROUTE         1   e 0.000    SLICE_75.F0 to    SLICE_44.D0 un69_pixelclocklto6_d
CTOF_DEL    ---     0.382    SLICE_44.D0 to    SLICE_44.F0 SLICE_44
ROUTE         1   e 0.000    SLICE_44.F0 to    SLICE_14.D0 un65_pixelclock_5Z0Z_1
CTOF_DEL    ---     0.382    SLICE_14.D0 to    SLICE_14.F0 SLICE_14
ROUTE         1   e 0.000    SLICE_14.F0 to   SLICE_14.DI0 VGAdena_0_sqmuxa_1 (to clk_c)
                  --------
                    6.498   (100.0% logic, 0.0% route), 15 logic levels.

Report:  149.768MHz is the maximum frequency for this preference.

Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY PORT "clk" 86.866000 MHz ;    |   86.866 MHz|  521.376 MHz|     0
                                        |             |             |
FREQUENCY NET "clk_c" 86.866000 MHz ;   |   86.866 MHz|  149.768 MHz|    15
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Timing summary:
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 19091 paths, 1 nets, and 563 connections (97.4% coverage)

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