5_1.par

用lattice XP3 demo板设计的VGA信号发生器

Lattice Place and Route Report for Design "videogenerator_map.ncd"
Sat Jun 16 17:34:48 2007

PAR: Place And Route ispLever_v61_PROD_Build (37).
Command line: C:/ispTOOLS6_1/ispfpga\bin\nt\par -f videogenerator.p2t videogenerator_map.ncd
videogenerator.dir videogenerator.prf
Preference file: videogenerator.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file videogenerator_map.ncd.
Design name: VideoGenerator
NCD version: 3.2
Vendor:      LATTICE
Device:      LFXP3C
Package:     PQFP208
Speed:       3
Loading device for application par from file 'mg5g19x26.nph' in environment
C:/ispTOOLS6_1/ispfpga.
Package: Version 1.40, Status: FINAL
Speed Hardware Data: version 9.999


Ignore Preference Error(s):  Yes
Dumping design to file C:/DOCUME~1/    /LOCALS~1/Temp/neo_2.
Device utilization summary:


   PIO               23/160          14% used
                     23/136          16% bonded

   IOLOGIC            6/160           3% used
   SLICE             83/1536          5% used



Number of Signals: 203
Number of Connections: 578
The following 1 signal is selected to use the primary clock routing resource:
    clk_c (driver: clk, clk load #: 35)

WARNING - par: Signal <clk_c> is selected to use Primary clock resources;
          however its driver comp <clk> is located at <20>, which is not a
          dedicated pin for connecting to Primary clock resources.  General
          routing has to be used to route this signal, and it may suffer
          from excessive delay or skew.
No signal is selected as DCS clock.

The following 1 signal is selected to use the secondary clock routing resource:
    pixelClockZ0 (driver: SLICE_42, clk load #: 0, sr load #: 0, ce load #: 26)

No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
.........
Finished Placer Phase 0.  REAL time: 5 secs 

Starting Placer Phase 1.
Placer score = 556782.
.........................
Placer score = 42482.
Finished Placer Phase 1.  REAL time: 37 secs 

Starting Placer Phase 2.
.
Placer score =  38066
Finished Placer Phase 2.  REAL time: 38 secs 


------------------ Clock Report ------------------

Global Clock Resources:
  CLK_PIN    : 0 out of 4 (0%)
  General PIO: 1 out of 160 (0%)
  PLL        : 0 out of 2 (0%)
  DCS        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "clk_c" from PIO "20", driver "clk", clk load = 35
  SECONDARY "pixelClockZ0" from ROUTING "R18C13A.Q0", driver "SLICE_42", clk load = 0, ce load = 26, sr load = 0

  PRIMARY  : 1 out of 4 (25%)
     DCS   : 0 out of 2 (0%)
  SECONDARY: 1 out of 4 (25%)

--------------- End of Clock Report ---------------


Total placer CPU time: 38 secs 

Dumping design to file videogenerator.dir/5_1.ncd.

0 connections routed; 578 unrouted.
Starting router resource preassignment
Clock Skew Minimization: OFF
WARNING - par: The driver of primary clock net clk_c is not placed on one
          of the PIO sites which are dedicated for primary clocks.  This
          primary clock will be routed to a H-spine through general routing
          resource or be routed as secondary clock and may suffer from
          excessive delay or skew.
Completed router resource preassignment. Real time: 43 secs 
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
578 successful; 0 unrouted; (16242093) real time: 47 secs 
Dumping design to file videogenerator.dir/5_1.ncd.
End of iteration 2
578 successful; 0 unrouted; (16230116) real time: 57 secs 
Dumping design to file videogenerator.dir/5_1.ncd.
End of iteration 3
578 successful; 0 unrouted; (16228898) real time: 1 mins 13 secs 
Dumping design to file videogenerator.dir/5_1.ncd.
End of iteration 4
578 successful; 0 unrouted; (16228898) real time: 1 mins 26 secs 
End of iteration 5
578 successful; 0 unrouted; (16228898) real time: 1 mins 34 secs 
End of iteration 6
578 successful; 0 unrouted; (16228898) real time: 1 mins 41 secs 
Giving up.
Total CPU time 1 mins 40 secs 
Total REAL time: 1 mins 41 secs 
Completely routed.
End of route.  578 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.
Timing score: 16228898 

Total REAL time to completion: 1 mins 42 secs 


All signals are completely routed.


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