videogenerator.testbench

用lattice XP3 demo板设计的VGA信号发生器

//----------------------------------------------------------------------
// Automatically Generated Test Bench -- Jagadeesh Vasudevamurthy
// Generated on Sat Jun 16 17:34:06 2007

// To prove RTL and Mapped circuit are equivalent for Altera do the following
// rm -rf inca_libs
// SET Q=X:/Altera/quartus_II60_pc 
// SET ATOMS=stratixii_atoms.v 
// ncverilog +licq_all VideoGenerator.vt  VideoGenerator.v  VideoGenerator.vm  -v %Q%/eda/sim_lib/nopli.v -v %Q%/eda/sim_lib/220model.v -v %Q%/eda/sim_lib/%ATOMS% -v %Q%/eda/sim_lib/altera_mf.v

// To prove RTL and Mapped circuit are equivalent for Xilinx do the following
// rm -rf inca_libs
// ncverilog  +nclicq VideoGenerator.vt  VideoGenerator.v  VideoGenerator.vm  X:/Xilinx/m82i/verilog/src/glbl.v  -y X:/Xilinx/m82i/verilog/src/unisims +libext+.v
//----------------------------------------------------------------------
`timescale 100 ps/100 ps
`define jag 1
module test_bench;
    parameter CLKPER = 1000;
    parameter NUMSIM = 1000;

    reg clk;
    reg UARTrx;
    wire UARTtx;
    wire UARTtx_rtl;
    wire  [1:0] VGAr;
    wire  [1:0] VGAr_rtl;
    wire  [1:0] VGAg;
    wire  [1:0] VGAg_rtl;
    wire  [1:0] VGAb;
    wire  [1:0] VGAb_rtl;
    wire VGAh_cs;
    wire VGAh_cs_rtl;
    wire VGAv;
    wire VGAv_rtl;
    wire VGAdena;
    wire VGAdena_rtl;
    wire  [3:0] NUMlocation;
    wire  [3:0] NUMlocation_rtl;
    wire  [7:0] NUMdata;
    wire  [7:0] NUMdata_rtl;
    reg key;

    integer i;
    integer numerrors;
    integer vecnum;

    VideoGenerator_rtl reference(.UARTrx(UARTrx),.key(key),.clk(clk),.UARTtx(UARTtx_rtl),.VGAr(VGAr_rtl),.VGAg(VGAg_rtl),.VGAb(VGAb_rtl),.VGAh_cs(VGAh_cs_rtl),.VGAv(VGAv_rtl),.VGAdena(VGAdena_rtl),.NUMlocation(NUMlocation_rtl),.NUMdata(NUMdata_rtl));
    VideoGenerator         impl(.UARTrx(UARTrx),.key(key),.clk(clk),.UARTtx(UARTtx),.VGAr(VGAr),.VGAg(VGAg),.VGAb(VGAb),.VGAh_cs(VGAh_cs),.VGAv(VGAv),.VGAdena(VGAdena),.NUMlocation(NUMlocation),.NUMdata(NUMdata));

    initial clk = 0;
    always #(CLKPER / 2) clk = ~clk;

    initial
    begin
        vecnum = 0;
        numerrors = 0;

        $display("Beginning Simulation..."); 
        $display("         vector UARTrx key UARTtx_rtl VGAr_rtl VGAg_rtl VGAb_rtl VGAh_cs_rtl VGAv_rtl VGAdena_rtl NUMlocation_rtl NUMdata_rtl UARTtx VGAr VGAg VGAb VGAh_cs VGAv VGAdena NUMlocation NUMdata ");   
    end
    always 
    begin 

        @(posedge clk);
            clk = ~clk;
            UARTrx = $random;
            key = $random;

//------------comparing 0 output UARTtx-----------
        @(negedge clk);
            if (UARTtx_rtl == UARTtx)
                begin
                    $display(" %d %d %d %d %d ", vecnum,UARTrx, key, UARTtx_rtl, UARTtx);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(UARTtx ^ UARTtx) === 1'bx) && (|(UARTtx_rtl ^ UARTtx) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d ", vecnum,UARTrx, key, UARTtx_rtl, UARTtx);
                    end
                end
//------------comparing 1 output VGAr-----------
        @(negedge clk);
            if (VGAr_rtl == VGAr)
                begin
                    $display(" %d %d %d %d %d ", vecnum,UARTrx, key, VGAr_rtl, VGAr);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(VGAr ^ VGAr) === 1'bx) && (|(VGAr_rtl ^ VGAr) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d ", vecnum,UARTrx, key, VGAr_rtl, VGAr);
                    end
                end
//------------comparing 2 output VGAg-----------
        @(negedge clk);
            if (VGAg_rtl == VGAg)
                begin
                    $display(" %d %d %d %d %d ", vecnum,UARTrx, key, VGAg_rtl, VGAg);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(VGAg ^ VGAg) === 1'bx) && (|(VGAg_rtl ^ VGAg) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d ", vecnum,UARTrx, key, VGAg_rtl, VGAg);
                    end
                end
//------------comparing 3 output VGAb-----------
        @(negedge clk);
            if (VGAb_rtl == VGAb)
                begin
                    $display(" %d %d %d %d %d ", vecnum,UARTrx, key, VGAb_rtl, VGAb);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(VGAb ^ VGAb) === 1'bx) && (|(VGAb_rtl ^ VGAb) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d ", vecnum,UARTrx, key, VGAb_rtl, VGAb);
                    end
                end
//------------comparing 4 output VGAh_cs-----------
        @(negedge clk);
            if (VGAh_cs_rtl == VGAh_cs)
                begin
                    $display(" %d %d %d %d %d ", vecnum,UARTrx, key, VGAh_cs_rtl, VGAh_cs);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(VGAh_cs ^ VGAh_cs) === 1'bx) && (|(VGAh_cs_rtl ^ VGAh_cs) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d ", vecnum,UARTrx, key, VGAh_cs_rtl, VGAh_cs);
                    end
                end
//------------comparing 5 output VGAv-----------
        @(negedge clk);
            if (VGAv_rtl == VGAv)
                begin
                    $display(" %d %d %d %d %d ", vecnum,UARTrx, key, VGAv_rtl, VGAv);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(VGAv ^ VGAv) === 1'bx) && (|(VGAv_rtl ^ VGAv) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d ", vecnum,UARTrx, key, VGAv_rtl, VGAv);
                    end
                end
//------------comparing 6 output VGAdena-----------
        @(negedge clk);
            if (VGAdena_rtl == VGAdena)
                begin
                    $display(" %d %d %d %d %d ", vecnum,UARTrx, key, VGAdena_rtl, VGAdena);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(VGAdena ^ VGAdena) === 1'bx) && (|(VGAdena_rtl ^ VGAdena) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d ", vecnum,UARTrx, key, VGAdena_rtl, VGAdena);
                    end
                end
//------------comparing 7 output NUMlocation-----------
        @(negedge clk);
            if (NUMlocation_rtl == NUMlocation)
                begin
                    $display(" %d %d %d %d %d ", vecnum,UARTrx, key, NUMlocation_rtl, NUMlocation);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(NUMlocation ^ NUMlocation) === 1'bx) && (|(NUMlocation_rtl ^ NUMlocation) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d ", vecnum,UARTrx, key, NUMlocation_rtl, NUMlocation);
                    end
                end
//------------comparing 8 output NUMdata-----------
        @(negedge clk);
            if (NUMdata_rtl == NUMdata)
                begin
                    $display(" %d %d %d %d %d ", vecnum,UARTrx, key, NUMdata_rtl, NUMdata);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(NUMdata ^ NUMdata) === 1'bx) && (|(NUMdata_rtl ^ NUMdata) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d ", vecnum,UARTrx, key, NUMdata_rtl, NUMdata);
                    end
                end
//------------Reporting Errors-----------
        vecnum = vecnum + 1;
        if (vecnum >= NUMSIM)
        begin
            case (numerrors)
                0 : $display("Good! End of Good Simulation."); 
                default : $display("%0d ERRORS! End of Faulty Simulation.", numerrors); 
            endcase
            #1000 $finish; 
        end
    end
endmodule