ifftram.vhd

VHDL程序设计的RAM存储器

--package iq_array is
  --type array_iq is array(1 downto 0) of std_logic_vector(16 downto 0);
--end iq_array;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity ifftram is
  generic(POINT: natural:=128;
	       Dwidth: natural:=16;
	       Awidth:	natural:=7);
  port (clkin   : in  std_logic;
        wen     : in  std_logic;
        addrin  : in  std_logic_vector(Awidth-1 downto 0);
        din     : in  std_logic_vector(Dwidth-1 downto 0);
        clkout  : in  std_logic;
        addrout : in  std_logic_vector(Awidth-1 downto 0);
        dout    : out std_logic_vector(Dwidth-1 downto 0));
end ifftram;

architecture Behavioral of ifftram is
  type ram_memtype is array (POINT-1 downto 0) of std_logic_vector(Dwidth-1 downto 0);
  signal mem : ram_memtype := (others => (others => '0'));
  signal addrb_reg: std_logic_vector(Awidth-1 downto 0);
begin
	wr: process( clkin )
	begin
		if rising_edge(clkin) then
			if wen = '1' then
				mem(conv_integer(addrin))<= din;
			end if;
		end if;
	end process wr;
	rd: process( clkout )
	begin
		if rising_edge(clkout) then
			addrb_reg<= addrout;
		end if;
    end process rd;
   dout <= mem(conv_integer(addrb_reg));
end Behavioral;