7064.map.qmsg

CPLD的例子程序2,EPM7064芯片,PC104扩展卡上应用

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 13 08:52:46 2007 " "Info: Processing started: Thu Sep 13 08:52:46 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off 7064 -c 7064 " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off 7064 -c 7064" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpld_7064.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cpld_7064.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cpld_7064-BEHAVE " "Info: Found design unit 1: cpld_7064-BEHAVE" {  } { { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 35 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cpld_7064 " "Info: Found entity 1: cpld_7064" {  } { { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "clkcounter1\[0\]~6 6 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: \"clkcounter1\[0\]~6\"" {  } { { "cpld_7064.vhd" "clkcounter1\[0\]~6" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 135 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "clkcounter2\[0\]~6 6 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: \"clkcounter2\[0\]~6\"" {  } { { "cpld_7064.vhd" "clkcounter2\[0\]~6" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 113 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 91 -1 0 } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 91 -1 0 } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 102 -1 0 } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 102 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_DISABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently disabled" { { "Warning" "WOPT_MLS_NODE_NAME" "LCLK~1 " "Warning: Node \"LCLK~1\"" {  } { { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 31 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "CLK_IN " "Info: Promoted clock signal driven by pin \"CLK_IN\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "3 " "Warning: Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "LRST " "Warning: No output dependent on input pin \"LRST\"" {  } { { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 16 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "CARL\[3\] " "Warning: No output dependent on input pin \"CARL\[3\]\"" {  } { { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 23 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "CARL\[2\] " "Warning: No output dependent on input pin \"CARL\[2\]\"" {  } { { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 23 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "198 " "Info: Implemented 198 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "24 " "Info: Implemented 24 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "25 " "Info: Implemented 25 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "11 " "Info: Implemented 11 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "106 " "Info: Implemented 106 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "32 " "Info: Implemented 32 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 13 08:52:54 2007 " "Info: Processing ended: Thu Sep 13 08:52:54 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}