7064.tan.qmsg

CPLD的例子程序2,EPM7064芯片,PC104扩展卡上应用

{ "Info" "ITDB_TH_RESULT" "IMREG\[6\] D\[6\] CLK_IN -2.000 ns register " "Info: th for register \"IMREG\[6\]\" (data pin = \"D\[6\]\", clock pin = \"CLK_IN\") is -2.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_IN destination 1.500 ns + Longest register " "Info: + Longest clock path from clock \"CLK_IN\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK_IN 1 CLK PIN_87 36 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 36; CLK Node = 'CLK_IN'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "" { CLK_IN } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns IMREG\[6\] 2 REG LC119 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC119; Fanout = 1; REG Node = 'IMREG\[6\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "0.000 ns" { CLK_IN IMREG[6] } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 161 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN IMREG[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out IMREG[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 161 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns D\[6\] 1 PIN PIN_21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_21; Fanout = 1; PIN Node = 'D\[6\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "" { D[6] } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns D\[6\]~4 2 COMB IO40 1 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = IO40; Fanout = 1; COMB Node = 'D\[6\]~4'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "0.500 ns" { D[6] D[6]~4 } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns IMREG\[6\] 3 REG LC119 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC119; Fanout = 1; REG Node = 'IMREG\[6\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "6.000 ns" { D[6]~4 IMREG[6] } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 161 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "6.500 ns" { D[6] D[6]~4 IMREG[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.500 ns" { D[6] D[6]~4 IMREG[6] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN IMREG[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out IMREG[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "6.500 ns" { D[6] D[6]~4 IMREG[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.500 ns" { D[6] D[6]~4 IMREG[6] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}
{ "Info" "ITAN_REQUIREMENTS_MET" "" "Info: All timing requirements were met. See Report window for more details." {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 13 08:53:05 2007 " "Info: Processing ended: Thu Sep 13 08:53:05 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}