7064.tan.qmsg

CPLD的例子程序2,EPM7064芯片,PC104扩展卡上应用

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "CLK_IN register div1\[4\] register lpm_counter:clkcounter1_rtl_0\|dffs\[0\] 5.0 ns " "Info: Minimum slack time is 5.0 ns for clock \"CLK_IN\" between source register \"div1\[4\]\" and destination register \"lpm_counter:clkcounter1_rtl_0\|dffs\[0\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Shortest register register " "Info: + Shortest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div1\[4\] 1 REG LC34 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC34; Fanout = 19; REG Node = 'div1\[4\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "" { div1[4] } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 91 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns lpm_counter:clkcounter1_rtl_0\|dffs\[0\] 2 REG LC110 64 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC110; Fanout = 64; REG Node = 'lpm_counter:clkcounter1_rtl_0\|dffs\[0\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "6.000 ns" { div1[4] lpm_counter:clkcounter1_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns 83.33 % " "Info: Total cell delay = 5.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 16.67 % " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "6.000 ns" { div1[4] lpm_counter:clkcounter1_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { div1[4] lpm_counter:clkcounter1_rtl_0|dffs[0] } { 0.0ns 1.0ns } { 0.0ns 5.0ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "1.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 1.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK_IN 25.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLK_IN\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK_IN 25.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLK_IN\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Source 0.000 ns 0 degrees " "Info: Clock offset from Source is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Destination 0.000 ns 0 degrees " "Info: Clock offset from Destination is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock" {  } {  } 0}  } {  } 0} { "Info" "ITDB_HOLD_UNCERTAINTY" "0.000 ns " "Info: Clock hold uncertainty between source and destination is 0.000 ns" {  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_IN destination 1.500 ns + Longest register " "Info: + Longest clock path from clock \"CLK_IN\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK_IN 1 CLK PIN_87 36 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 36; CLK Node = 'CLK_IN'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "" { CLK_IN } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns lpm_counter:clkcounter1_rtl_0\|dffs\[0\] 2 REG LC110 64 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC110; Fanout = 64; REG Node = 'lpm_counter:clkcounter1_rtl_0\|dffs\[0\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "0.000 ns" { CLK_IN lpm_counter:clkcounter1_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN lpm_counter:clkcounter1_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out lpm_counter:clkcounter1_rtl_0|dffs[0] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 1.5ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_IN source 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK_IN\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK_IN 1 CLK PIN_87 36 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 36; CLK Node = 'CLK_IN'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "" { CLK_IN } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns div1\[4\] 2 REG LC34 19 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC34; Fanout = 19; REG Node = 'div1\[4\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "0.000 ns" { CLK_IN div1[4] } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 91 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN div1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out div1[4] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 1.5ns 0.0ns } } }  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN lpm_counter:clkcounter1_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out lpm_counter:clkcounter1_rtl_0|dffs[0] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 1.5ns 0.0ns } } } { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN div1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out div1[4] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 1.5ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" {  } { { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 91 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN lpm_counter:clkcounter1_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out lpm_counter:clkcounter1_rtl_0|dffs[0] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 1.5ns 0.0ns } } } { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN div1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out div1[4] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 1.5ns 0.0ns } } }  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "6.000 ns" { div1[4] lpm_counter:clkcounter1_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { div1[4] lpm_counter:clkcounter1_rtl_0|dffs[0] } { 0.0ns 1.0ns } { 0.0ns 5.0ns } } } { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN lpm_counter:clkcounter1_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out lpm_counter:clkcounter1_rtl_0|dffs[0] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 1.5ns 0.0ns } } } { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN div1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out div1[4] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 1.5ns 0.0ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "IMREG\[6\] D\[6\] CLK_IN 7.000 ns register " "Info: tsu for register \"IMREG\[6\]\" (data pin = \"D\[6\]\", clock pin = \"CLK_IN\") is 7.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest pin register " "Info: + Longest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns D\[6\] 1 PIN PIN_21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_21; Fanout = 1; PIN Node = 'D\[6\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "" { D[6] } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns D\[6\]~4 2 COMB IO40 1 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = IO40; Fanout = 1; COMB Node = 'D\[6\]~4'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "0.500 ns" { D[6] D[6]~4 } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns IMREG\[6\] 3 REG LC119 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC119; Fanout = 1; REG Node = 'IMREG\[6\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "6.000 ns" { D[6]~4 IMREG[6] } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 161 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "6.500 ns" { D[6] D[6]~4 IMREG[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.500 ns" { D[6] D[6]~4 IMREG[6] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 161 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_IN destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK_IN\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK_IN 1 CLK PIN_87 36 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 36; CLK Node = 'CLK_IN'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "" { CLK_IN } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns IMREG\[6\] 2 REG LC119 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC119; Fanout = 1; REG Node = 'IMREG\[6\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "0.000 ns" { CLK_IN IMREG[6] } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 161 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN IMREG[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out IMREG[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "6.500 ns" { D[6] D[6]~4 IMREG[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.500 ns" { D[6] D[6]~4 IMREG[6] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN IMREG[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out IMREG[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK_IN IRQ IMREG\[5\] 21.000 ns register " "Info: tco from clock \"CLK_IN\" to destination pin \"IRQ\" through register \"IMREG\[5\]\" is 21.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_IN source 1.500 ns + Longest register " "Info: + Longest clock path from clock \"CLK_IN\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK_IN 1 CLK PIN_87 36 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 36; CLK Node = 'CLK_IN'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "" { CLK_IN } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns IMREG\[5\] 2 REG LC106 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC106; Fanout = 1; REG Node = 'IMREG\[5\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "0.000 ns" { CLK_IN IMREG[5] } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 161 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN IMREG[5] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out IMREG[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 161 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.500 ns + Longest register pin " "Info: + Longest register to pin delay is 17.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns IMREG\[5\] 1 REG LC106 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC106; Fanout = 1; REG Node = 'IMREG\[5\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "" { IMREG[5] } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 161 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.000 ns IRQ~33bal 2 COMB LC48 5 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC48; Fanout = 5; COMB Node = 'IRQ~33bal'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "8.000 ns" { IMREG[5] IRQ~33bal } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 16.000 ns IRQ~38 3 COMB LC17 1 " "Info: 3: + IC(1.000 ns) + CELL(7.000 ns) = 16.000 ns; Loc. = LC17; Fanout = 1; COMB Node = 'IRQ~38'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "8.000 ns" { IRQ~33bal IRQ~38 } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 17.500 ns IRQ 4 PIN PIN_14 0 " "Info: 4: + IC(0.000 ns) + CELL(1.500 ns) = 17.500 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'IRQ'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { IRQ~38 IRQ } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.500 ns 88.57 % " "Info: Total cell delay = 15.500 ns ( 88.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 11.43 % " "Info: Total interconnect delay = 2.000 ns ( 11.43 % )" {  } {  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "17.500 ns" { IMREG[5] IRQ~33bal IRQ~38 IRQ } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.500 ns" { IMREG[5] IRQ~33bal IRQ~38 IRQ } { 0.000ns 1.000ns 1.000ns 0.000ns } { 0.000ns 7.000ns 7.000ns 1.500ns } } }  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN IMREG[5] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out IMREG[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "17.500 ns" { IMREG[5] IRQ~33bal IRQ~38 IRQ } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.500 ns" { IMREG[5] IRQ~33bal IRQ~38 IRQ } { 0.000ns 1.000ns 1.000ns 0.000ns } { 0.000ns 7.000ns 7.000ns 1.500ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "OE D\[6\] 24.500 ns Longest " "Info: Longest tpd from source pin \"OE\" to destination pin \"D\[6\]\" is 24.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns OE 1 PIN PIN_30 9 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_30; Fanout = 9; PIN Node = 'OE'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "" { OE } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.500 ns INT_REG_RD~14 2 COMB LC46 2 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.500 ns; Loc. = LC46; Fanout = 2; COMB Node = 'INT_REG_RD~14'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "8.000 ns" { OE INT_REG_RD~14 } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 16.500 ns INT_REG_RD~16 3 COMB LC59 10 " "Info: 3: + IC(1.000 ns) + CELL(7.000 ns) = 16.500 ns; Loc. = LC59; Fanout = 10; COMB Node = 'INT_REG_RD~16'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "8.000 ns" { INT_REG_RD~14 INT_REG_RD~16 } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 24.500 ns D\[6\] 4 PIN PIN_21 0 " "Info: 4: + IC(1.000 ns) + CELL(7.000 ns) = 24.500 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'D\[6\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "8.000 ns" { INT_REG_RD~16 D[6] } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.500 ns 87.76 % " "Info: Total cell delay = 21.500 ns ( 87.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 12.24 % " "Info: Total interconnect delay = 3.000 ns ( 12.24 % )" {  } {  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "24.500 ns" { OE INT_REG_RD~14 INT_REG_RD~16 D[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "24.500 ns" { OE OE~out INT_REG_RD~14 INT_REG_RD~16 D[6] } { 0.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 7.000ns 7.000ns 7.000ns } } }  } 0}