7064.tan.qmsg

CPLD的例子程序2,EPM7064芯片,PC104扩展卡上应用

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CARL\[0\] " "Info: No valid register-to-register data paths exist for clock \"CARL\[0\]\"" {  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CARL\[1\] " "Info: No valid register-to-register data paths exist for clock \"CARL\[1\]\"" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLK_IN register div1\[4\] register lpm_counter:clkcounter1_rtl_0\|dffs\[3\] 6.2 ns " "Info: Slack time is 6.2 ns for clock \"CLK_IN\" between source register \"div1\[4\]\" and destination register \"lpm_counter:clkcounter1_rtl_0\|dffs\[3\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "53.19 MHz 18.8 ns " "Info: Fmax is 53.19 MHz (period= 18.8 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "21.000 ns + Largest register register " "Info: + Largest register to register requirement is 21.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "25.000 ns + " "Info: + Setup relationship between source and destination is 25.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 25.000 ns " "Info: + Latch edge is 25.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK_IN 25.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLK_IN\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK_IN 25.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLK_IN\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Source 0.000 ns 0 degrees " "Info: Clock offset from Source is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Destination 0.000 ns 0 degrees " "Info: Clock offset from Destination is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock" {  } {  } 0}  } {  } 0} { "Info" "ITDB_SETUP_UNCERTAINTY" "0.000 ns " "Info: Clock setup uncertainty between source and destination is 0.000 ns" {  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_IN destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_IN\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK_IN 1 CLK PIN_87 36 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 36; CLK Node = 'CLK_IN'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "" { CLK_IN } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns lpm_counter:clkcounter1_rtl_0\|dffs\[3\] 2 REG LC53 32 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC53; Fanout = 32; REG Node = 'lpm_counter:clkcounter1_rtl_0\|dffs\[3\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "0.000 ns" { CLK_IN lpm_counter:clkcounter1_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN lpm_counter:clkcounter1_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out lpm_counter:clkcounter1_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_IN source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"CLK_IN\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK_IN 1 CLK PIN_87 36 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 36; CLK Node = 'CLK_IN'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "" { CLK_IN } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns div1\[4\] 2 REG LC34 19 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC34; Fanout = 19; REG Node = 'div1\[4\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "0.000 ns" { CLK_IN div1[4] } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 91 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN div1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out div1[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN lpm_counter:clkcounter1_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out lpm_counter:clkcounter1_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN div1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out div1[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" {  } { { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 91 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns - " "Info: - Micro setup delay of destination is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN lpm_counter:clkcounter1_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out lpm_counter:clkcounter1_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN div1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out div1[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.800 ns - Longest register register " "Info: - Longest register to register delay is 14.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div1\[4\] 1 REG LC34 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC34; Fanout = 19; REG Node = 'div1\[4\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "" { div1[4] } "NODE_NAME" } "" } } { "cpld_7064.vhd" "" { Text "E:/Communication Maneger/CPLD/V2.1_OK/7128/cpld_7064.vhd" 91 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns reduce_nor~63 2 COMB LC111 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC111; Fanout = 1; COMB Node = 'reduce_nor~63'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "6.000 ns" { div1[4] reduce_nor~63 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 8.800 ns reduce_nor~53 3 COMB LC112 1 " "Info: 3: + IC(0.000 ns) + CELL(2.800 ns) = 8.800 ns; Loc. = LC112; Fanout = 1; COMB Node = 'reduce_nor~53'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "2.800 ns" { reduce_nor~63 reduce_nor~53 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.800 ns lpm_counter:clkcounter1_rtl_0\|dffs\[3\] 4 REG LC53 32 " "Info: 4: + IC(1.000 ns) + CELL(5.000 ns) = 14.800 ns; Loc. = LC53; Fanout = 32; REG Node = 'lpm_counter:clkcounter1_rtl_0\|dffs\[3\]'" {  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "6.000 ns" { reduce_nor~53 lpm_counter:clkcounter1_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.800 ns 86.49 % " "Info: Total cell delay = 12.800 ns ( 86.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 13.51 % " "Info: Total interconnect delay = 2.000 ns ( 13.51 % )" {  } {  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "14.800 ns" { div1[4] reduce_nor~63 reduce_nor~53 lpm_counter:clkcounter1_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "14.800 ns" { div1[4] reduce_nor~63 reduce_nor~53 lpm_counter:clkcounter1_rtl_0|dffs[3] } { 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 5.000ns 2.800ns 5.000ns } } }  } 0}  } { { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN lpm_counter:clkcounter1_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out lpm_counter:clkcounter1_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "1.500 ns" { CLK_IN div1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { CLK_IN CLK_IN~out div1[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" "" { Report "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064_cmp.qrpt" Compiler "7064" "UNKNOWN" "V1" "E:/Communication Maneger/CPLD/V2.1_OK/7128/db/7064.quartus_db" { Floorplan "E:/Communication Maneger/CPLD/V2.1_OK/7128/" "" "14.800 ns" { div1[4] reduce_nor~63 reduce_nor~53 lpm_counter:clkcounter1_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "14.800 ns" { div1[4] reduce_nor~63 reduce_nor~53 lpm_counter:clkcounter1_rtl_0|dffs[3] } { 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 5.000ns 2.800ns 5.000ns } } }  } 0}