7064.fit.eqn

CPLD的例子程序2,EPM7064芯片,PC104扩展卡上应用

--A1L47 is INT_REG_RD~14 at LC46
A1L47_p1_out = !OE & A[2] & !A[1] & !A[4] & !A[3] & !A[5] & !CS;
A1L47_or_out = A1L47_p1_out;
A1L47 = !(A1L47_or_out);


--A1L141 is RDY[7]~16 at LC41
A1L141_or_out = RDY[7];
A1L141 = A1L141_or_out;


--A1L931 is RDY[6]~18 at LC40
A1L931_or_out = RDY[6];
A1L931 = A1L931_or_out;


--A1L731 is RDY[5]~20 at LC38
A1L731_or_out = RDY[5];
A1L731 = A1L731_or_out;


--A1L531 is RDY[4]~22 at LC37
A1L531_or_out = RDY[4];
A1L531 = A1L531_or_out;


--A1L331 is RDY[3]~24 at LC35
A1L331_or_out = RDY[3];
A1L331 = A1L331_or_out;


--A1L131 is RDY[2]~26 at LC33
A1L131_or_out = RDY[2];
A1L131 = A1L131_or_out;


--A1L921 is RDY[1]~28 at LC64
A1L921_or_out = RDY[1];
A1L921 = A1L921_or_out;


--A1L721 is RDY[0]~30 at LC62
A1L721_or_out = RDY[0];
A1L721 = A1L721_or_out;


--CARL_INT0 is CARL_INT0 at LC43
CARL_INT0_or_out = GND;
CARL_INT0_reg_input = CARL_INT0_or_out;
CARL_INT0 = DFFE(CARL_INT0_reg_input, CARL[0], , CRST, );


--CARL_INT1 is CARL_INT1 at LC45
CARL_INT1_or_out = GND;
CARL_INT1_reg_input = CARL_INT1_or_out;
CARL_INT1 = DFFE(CARL_INT1_reg_input, CARL[1], , CRST, );


--A1L3 is A[1]~631 at LC113
A1L3_or_out = A[1];
A1L3 = A1L3_or_out;


--B1_dffs[0] is lpm_counter:clkcounter1_rtl_0|dffs[0] at LC110
B1_dffs[0]_p0_out = !B1_dffs[0] & !div1[5] & B1_dffs[5];
B1_dffs[0]_p1_out = !div1[3] & B1_dffs[3] & !B1_dffs[0];
B1_dffs[0]_p2_out = !B1_dffs[0] & !div1[4] & !B1_dffs[4];
B1_dffs[0]_p3_out = !B1_dffs[0] & div1[4] & B1_dffs[4];
B1_dffs[0]_p4_out = !B1_dffs[0] & div1[5] & !B1_dffs[5];
B1_dffs[0]_or_out = B1L5 # B1_dffs[0]_p0_out # B1_dffs[0]_p1_out # B1_dffs[0]_p2_out # B1_dffs[0]_p3_out # B1_dffs[0]_p4_out;
B1_dffs[0]_reg_input = B1_dffs[0]_or_out;
B1_dffs[0] = DFFE(B1_dffs[0]_reg_input, GLOBAL(CLK_IN), , , );


--B2_dffs[0] is lpm_counter:clkcounter2_rtl_1|dffs[0] at LC76
B2_dffs[0]_p0_out = !B2_dffs[0] & !div2[5] & B2_dffs[5];
B2_dffs[0]_p1_out = !div2[3] & B2_dffs[3] & !B2_dffs[0];
B2_dffs[0]_p2_out = !B2_dffs[0] & !div2[4] & !B2_dffs[4];
B2_dffs[0]_p3_out = !B2_dffs[0] & div2[4] & B2_dffs[4];
B2_dffs[0]_p4_out = !B2_dffs[0] & div2[5] & !B2_dffs[5];
B2_dffs[0]_or_out = B2L5 # B2_dffs[0]_p0_out # B2_dffs[0]_p1_out # B2_dffs[0]_p2_out # B2_dffs[0]_p3_out # B2_dffs[0]_p4_out;
B2_dffs[0]_reg_input = B2_dffs[0]_or_out;
B2_dffs[0] = DFFE(B2_dffs[0]_reg_input, GLOBAL(CLK_IN), , , );


--A1L711 is OE429~340 at LC105
A1L711_p1_out = A[2] & !OE & !CS429 & !A[4] & !A[3] & !A[5];
A1L711_or_out = A1L711_p1_out;
A1L711 = !(A1L711_or_out);


--A1L811 is OE429~343 at LC107
A1L811_p1_out = !A[2] & !OE & !CS429 & !A[4] & !A[3] & !A[5];
A1L811_or_out = A1L811_p1_out;
A1L811 = !(A1L811_or_out);


--A1L911 is OE429~345 at LC93
A1L911_p1_out = !OE & !CS429 & A[4] & A[3] & A[2] & !A[5];
A1L911_or_out = A1L911_p1_out;
A1L911 = !(A1L911_or_out);


--A1L021 is OE429~348 at LC30
A1L021_p1_out = A[2] & !OE & !CS429 & !A[5] & A[4] & !A[3];
A1L021_or_out = A1L021_p1_out;
A1L021 = !(A1L021_or_out);


--A1L121 is OE429~351 at LC117
A1L121_p1_out = !OE & !CS429 & !A[5] & A[2] & !A[4] & A[3];
A1L121_or_out = A1L121_p1_out;
A1L121 = !(A1L121_or_out);


--A1L221 is OE429~354 at LC118
A1L221_p1_out = !A[2] & !OE & !CS429 & !A[5] & !A[4] & A[3];
A1L221_or_out = A1L221_p1_out;
A1L221 = !(A1L221_or_out);


--A1L49 is LD429~737 at LC121
A1L49_p1_out = A[4] & A[3] & A[2] & !A[5] & !A[1] & !CS429 & !WR;
A1L49_or_out = A1L49_p1_out;
A1L49 = !(A1L49_or_out);


--A1L59 is LD429~740 at LC126
A1L59_p1_out = !CS429 & !WR & A[2] & !A[1] & !A[4] & !A[3] & !A[5];
A1L59_or_out = A1L59_p1_out;
A1L59 = !(A1L59_or_out);


--A1L69 is LD429~743 at LC128
A1L69_p1_out = !CS429 & !WR & !A[2] & !A[1] & !A[4] & !A[3] & !A[5];
A1L69_or_out = A1L69_p1_out;
A1L69 = !(A1L69_or_out);


--A1L79 is LD429~746 at LC101
A1L79_p1_out = A[2] & !A[4] & A[3] & A[5] & !A[1] & !CS429 & !WR;
A1L79_or_out = A1L79_p1_out;
A1L79 = !(A1L79_or_out);


--A1L321 is OE429~357 at LC91
A1L321_p1_out = A[3] & !OE & !CS429 & !A[5] & A[4] & !A[2];
A1L321_or_out = A1L321_p1_out;
A1L321 = !(A1L321_or_out);


--A1L421 is OE429~360 at LC29
A1L421_p1_out = !A[3] & !OE & !CS429 & !A[5] & A[4] & !A[2];
A1L421_or_out = A1L421_p1_out;
A1L421 = !(A1L421_or_out);


--A1L89 is LD429~749 at LC16
A1L89_p1_out = A[4] & !A[3] & A[2] & !A[5] & !A[1] & !CS429 & !WR;
A1L89_or_out = A1L89_p1_out;
A1L89 = !(A1L89_or_out);


--A1L99 is LD429~752 at LC14
A1L99_p1_out = !A[3] & A[4] & !A[2] & !A[5] & !A[1] & !CS429 & !WR;
A1L99_or_out = A1L99_p1_out;
A1L99 = !(A1L99_or_out);


--A1L001 is LD429~755 at LC13
A1L001_p1_out = !A[4] & A[3] & A[2] & !A[5] & !A[1] & !CS429 & !WR;
A1L001_or_out = A1L001_p1_out;
A1L001 = !(A1L001_or_out);


--B1_dffs[1] is lpm_counter:clkcounter1_rtl_0|dffs[1] at LC100
B1_dffs[1]_p0_out = !B1_dffs[0] & B1_dffs[1] & !div1[5] & B1_dffs[5];
B1_dffs[1]_p1_out = div1[4] & B1_dffs[4] & !B1_dffs[0] & B1_dffs[1];
B1_dffs[1]_p2_out = B1_dffs[0] & !B1_dffs[1] & div1[5] & !B1_dffs[5];
B1_dffs[1]_p3_out = !B1_dffs[0] & B1_dffs[1] & div1[5] & !B1_dffs[5];
B1_dffs[1]_p4_out = B1_dffs[0] & !B1_dffs[1] & !div1[5] & B1_dffs[5];
B1_dffs[1]_or_out = B1L9 # B1_dffs[1]_p0_out # B1_dffs[1]_p1_out # B1_dffs[1]_p2_out # B1_dffs[1]_p3_out # B1_dffs[1]_p4_out;
B1_dffs[1]_reg_input = B1_dffs[1]_or_out;
B1_dffs[1] = DFFE(B1_dffs[1]_reg_input, GLOBAL(CLK_IN), , , );


--B2_dffs[1] is lpm_counter:clkcounter2_rtl_1|dffs[1] at LC69
B2_dffs[1]_p0_out = !B2_dffs[0] & B2_dffs[1] & !div2[5] & B2_dffs[5];
B2_dffs[1]_p1_out = div2[4] & B2_dffs[4] & !B2_dffs[0] & B2_dffs[1];
B2_dffs[1]_p2_out = B2_dffs[0] & !B2_dffs[1] & div2[5] & !B2_dffs[5];
B2_dffs[1]_p3_out = !B2_dffs[0] & B2_dffs[1] & div2[5] & !B2_dffs[5];
B2_dffs[1]_p4_out = B2_dffs[0] & !B2_dffs[1] & !div2[5] & B2_dffs[5];
B2_dffs[1]_or_out = B2L9 # B2_dffs[1]_p0_out # B2_dffs[1]_p1_out # B2_dffs[1]_p2_out # B2_dffs[1]_p3_out # B2_dffs[1]_p4_out;
B2_dffs[1]_reg_input = B2_dffs[1]_or_out;
B2_dffs[1] = DFFE(B2_dffs[1]_reg_input, GLOBAL(CLK_IN), , , );


--A1L101 is LD429~758 at LC102
A1L101_p1_out = !A[3] & A[2] & !A[4] & A[5] & !A[1] & !CS429 & !WR;
A1L101_or_out = A1L101_p1_out;
A1L101 = !(A1L101_or_out);


--A1L201 is LD429~761 at LC123
A1L201_p1_out = A[4] & !A[2] & A[3] & !A[5] & !A[1] & !CS429 & !WR;
A1L201_or_out = A1L201_p1_out;
A1L201 = !(A1L201_or_out);


--A1L301 is LD429~764 at LC125
A1L301_p1_out = !A[4] & !A[2] & A[3] & !A[5] & !A[1] & !CS429 & !WR;
A1L301_or_out = A1L301_p1_out;
A1L301 = !(A1L301_or_out);


--A1L401 is LD429~767 at LC104
A1L401_p1_out = A[3] & !A[2] & !A[4] & A[5] & !A[1] & !CS429 & !WR;
A1L401_or_out = A1L401_p1_out;
A1L401 = !(A1L401_or_out);


--A1L501 is LD429~770 at LC120
A1L501_p1_out = !A[3] & !A[2] & !A[4] & A[5] & !A[1] & !CS429 & !WR;
A1L501_or_out = A1L501_p1_out;
A1L501 = !(A1L501_or_out);


--div1[3] is div1[3] at LC85
div1[3]_or_out = A1L53;
div1[3]_reg_input = div1[3]_or_out;
div1[3]_p3_out = A[2] & A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
div1[3] = DFFE(div1[3]_reg_input, GLOBAL(CLK_IN), CRST, , div1[3]_p3_out);


--div1[1] is div1[1] at LC92
div1[1]_or_out = A1L13;
div1[1]_reg_input = div1[1]_or_out;
div1[1]_p3_out = A[2] & A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
div1[1] = DFFE(div1[1]_reg_input, GLOBAL(CLK_IN), CRST, , div1[1]_p3_out);


--div1[0] is div1[0] at LC15
div1[0]_or_out = A1L92;
div1[0]_reg_input = div1[0]_or_out;
div1[0]_p3_out = A[2] & A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
div1[0] = DFFE(div1[0]_reg_input, GLOBAL(CLK_IN), CRST, , div1[0]_p3_out);


--div2[5] is div2[5] at LC5
div2[5]_or_out = A1L93;
div2[5]_reg_input = div2[5]_or_out;
div2[5]_p3_out = !A[2] & A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
div2[5] = DFFE(div2[5]_reg_input, GLOBAL(CLK_IN), CRST, , div2[5]_p3_out);


--div2[3] is div2[3] at LC89
div2[3]_or_out = A1L53;
div2[3]_reg_input = div2[3]_or_out;
div2[3]_p3_out = !A[2] & A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
div2[3] = DFFE(div2[3]_reg_input, GLOBAL(CLK_IN), CRST, , div2[3]_p3_out);


--div2[1] is div2[1] at LC84
div2[1]_or_out = A1L13;
div2[1]_reg_input = div2[1]_or_out;
div2[1]_p3_out = !A[2] & A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
div2[1] = DFFE(div2[1]_reg_input, GLOBAL(CLK_IN), CRST, , div2[1]_p3_out);


--div2[0] is div2[0] at LC4
div2[0]_or_out = A1L92;
div2[0]_reg_input = div2[0]_or_out;
div2[0]_p3_out = !A[2] & A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
div2[0] = DFFE(div2[0]_reg_input, GLOBAL(CLK_IN), CRST, , div2[0]_p3_out);


--IMREG[9] is IMREG[9] at LC90
IMREG[9]_or_out = A1L74;
IMREG[9]_reg_input = IMREG[9]_or_out;
IMREG[9]_p3_out = !A[2] & !A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
IMREG[9] = DFFE(IMREG[9]_reg_input, GLOBAL(CLK_IN), CRST, , IMREG[9]_p3_out);


--IMREG[8] is IMREG[8] at LC95
IMREG[8]_or_out = A1L54;
IMREG[8]_reg_input = IMREG[8]_or_out;
IMREG[8]_p3_out = !A[2] & !A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
IMREG[8] = DFFE(IMREG[8]_reg_input, GLOBAL(CLK_IN), CRST, , IMREG[8]_p3_out);


--IMREG[7] is IMREG[7] at LC114
IMREG[7]_or_out = A1L34;
IMREG[7]_reg_input = IMREG[7]_or_out;
IMREG[7]_p3_out = !A[2] & !A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
IMREG[7] = DFFE(IMREG[7]_reg_input, GLOBAL(CLK_IN), CRST, , IMREG[7]_p3_out);


--IMREG[6] is IMREG[6] at LC119
IMREG[6]_or_out = A1L14;
IMREG[6]_reg_input = IMREG[6]_or_out;
IMREG[6]_p3_out = !A[2] & !A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
IMREG[6] = DFFE(IMREG[6]_reg_input, GLOBAL(CLK_IN), CRST, , IMREG[6]_p3_out);


--IMREG[5] is IMREG[5] at LC106
IMREG[5]_or_out = A1L93;
IMREG[5]_reg_input = IMREG[5]_or_out;
IMREG[5]_p3_out = !A[2] & !A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
IMREG[5] = DFFE(IMREG[5]_reg_input, GLOBAL(CLK_IN), CRST, , IMREG[5]_p3_out);


--IMREG[4] is IMREG[4] at LC47
IMREG[4]_or_out = A1L73;
IMREG[4]_reg_input = IMREG[4]_or_out;
IMREG[4]_p3_out = !A[2] & !A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
IMREG[4] = DFFE(IMREG[4]_reg_input, GLOBAL(CLK_IN), CRST, , IMREG[4]_p3_out);


--IMREG[3] is IMREG[3] at LC96
IMREG[3]_or_out = A1L53;
IMREG[3]_reg_input = IMREG[3]_or_out;
IMREG[3]_p3_out = !A[2] & !A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
IMREG[3] = DFFE(IMREG[3]_reg_input, GLOBAL(CLK_IN), CRST, , IMREG[3]_p3_out);


--IMREG[2] is IMREG[2] at LC42
IMREG[2]_or_out = A1L33;
IMREG[2]_reg_input = IMREG[2]_or_out;
IMREG[2]_p3_out = !A[2] & !A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
IMREG[2] = DFFE(IMREG[2]_reg_input, GLOBAL(CLK_IN), CRST, , IMREG[2]_p3_out);


--IMREG[1] is IMREG[1] at LC94
IMREG[1]_or_out = A1L13;
IMREG[1]_reg_input = IMREG[1]_or_out;
IMREG[1]_p3_out = !A[2] & !A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
IMREG[1] = DFFE(IMREG[1]_reg_input, GLOBAL(CLK_IN), CRST, , IMREG[1]_p3_out);


--IMREG[0] is IMREG[0] at LC2
IMREG[0]_or_out = A1L92;
IMREG[0]_reg_input = IMREG[0]_or_out;
IMREG[0]_p3_out = !A[2] & !A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
IMREG[0] = DFFE(IMREG[0]_reg_input, GLOBAL(CLK_IN), CRST, , IMREG[0]_p3_out);


--div1[5] is div1[5] at LC103
div1[5]_or_out = A1L93;
div1[5]_reg_input = div1[5]_or_out;
div1[5]_p3_out = A[2] & A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
div1[5] = DFFE(div1[5]_reg_input, GLOBAL(CLK_IN), CRST, , div1[5]_p3_out);


--div1[4] is div1[4] at LC34
div1[4]_or_out = !A1L73;
div1[4]_reg_input = div1[4]_or_out;
div1[4]_p3_out = A[2] & A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
div1[4] = DFFE(div1[4]_reg_input, GLOBAL(CLK_IN), CRST, , div1[4]_p3_out);


--div1[2] is div1[2] at LC36
div1[2]_or_out = !A1L33;
div1[2]_reg_input = div1[2]_or_out;
div1[2]_p3_out = A[2] & A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
div1[2] = DFFE(div1[2]_reg_input, GLOBAL(CLK_IN), CRST, , div1[2]_p3_out);


--div2[4] is div2[4] at LC39
div2[4]_or_out = !A1L73;
div2[4]_reg_input = div2[4]_or_out;
div2[4]_p3_out = !A[2] & A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
div2[4] = DFFE(div2[4]_reg_input, GLOBAL(CLK_IN), CRST, , div2[4]_p3_out);


--div2[2] is div2[2] at LC44
div2[2]_or_out = !A1L33;
div2[2]_reg_input = div2[2]_or_out;
div2[2]_p3_out = !A[2] & A[1] & !A[4] & !A[3] & !A[5] & !WR & !CS;
div2[2] = DFFE(div2[2]_reg_input, GLOBAL(CLK_IN), CRST, , div2[2]_p3_out);


--A1L97 is IRQ~38 at LC17
A1L97_p1_out = A1L77 & A1L87;
A1L97_p0_out = A1L77 & A1L87 & IMREG[8] & !CARL_INT0;
A1L97_p2_out = A1L77 & A1L87 & IMREG[6] & !RDY[6];
A1L97_p3_out = A1L77 & A1L87 & IMREG[7] & !RDY[7];
A1L97_p4_out = A1L77 & A1L87 & IMREG[9] & !CARL_INT1;
A1L97_or_out = A1L97_p0_out # A1L97_p2_out # A1L97_p3_out # A1L97_p4_out;
A1L97 = A1L97_p1_out $ A1L97_or_out;


--B1L11 is lpm_counter:clkcounter1_rtl_0|dffs[2]~148 at SEXP49
B1L11 = EXP(div1[0] & div1[1] & div1[2]);


--B1L21 is lpm_counter:clkcounter1_rtl_0|dffs[2]~149 at SEXP53
B1L21 = EXP(!div1[0] & !div1[2]);


--B1L31 is lpm_counter:clkcounter1_rtl_0|dffs[2]~150 at SEXP63
B1L31 = EXP(!div1[1] & !div1[2]);


--B1L41 is lpm_counter:clkcounter1_rtl_0|dffs[2]~151 at SEXP61
B1L41 = EXP(B1_dffs[0] & B1_dffs[1]);


--B1_dffs[2] is lpm_counter:clkcounter1_rtl_0|dffs[2] at LC52
B1_dffs[2]_p0_out = B1L41 & B1_dffs[2] & !div1[5] & B1_dffs[5];
B1_dffs[2]_p1_out = B1L41 & !div1[3] & B1_dffs[3] & B1_dffs[2];
B1_dffs[2]_p2_out = B1L41 & B1_dffs[2] & !div1[4] & !B1_dffs[4];
B1_dffs[2]_p3_out = B1L41 & B1_dffs[2] & div1[4] & B1_dffs[4];
B1_dffs[2]_p4_out = B1L41 & B1_dffs[2] & div1[5] & !B1_dffs[5];
B1_dffs[2]_or_out = B1L71 # B1_dffs[2]_p0_out # B1_dffs[2]_p1_out # B1_dffs[2]_p2_out # B1_dffs[2]_p3_out # B1_dffs[2]_p4_out;
B1_dffs[2]_reg_input = B1_dffs[2]_or_out;
B1_dffs[2] = DFFE(B1_dffs[2]_reg_input, GLOBAL(CLK_IN), , , );


--B2L11 is lpm_counter:clkcounter2_rtl_1|dffs[2]~148 at SEXP79
B2L11 = EXP(div2[0] & div2[1] & div2[2]);


--B2L21 is lpm_counter:clkcounter2_rtl_1|dffs[2]~149 at SEXP74
B2L21 = EXP(!div2[0] & !div2[2]);


--B2L31 is lpm_counter:clkcounter2_rtl_1|dffs[2]~150 at SEXP70
B2L31 = EXP(!div2[1] & !div2[2]);


--B2L41 is lpm_counter:clkcounter2_rtl_1|dffs[2]~151 at SEXP65
B2L41 = EXP(B2_dffs[0] & B2_dffs[1]);


--B2_dffs[2] is lpm_counter:clkcounter2_rtl_1|dffs[2] at LC73
B2_dffs[2]_p0_out = B2L41 & B2_dffs[2] & !div2[5] & B2_dffs[5];
B2_dffs[2]_p1_out = B2L41 & !div2[3] & B2_dffs[3] & B2_dffs[2];
B2_dffs[2]_p2_out = B2L41 & B2_dffs[2] & !div2[4] & !B2_dffs[4];
B2_dffs[2]_p3_out = B2L41 & B2_dffs[2] & div2[4] & B2_dffs[4];
B2_dffs[2]_p4_out = B2L41 & B2_dffs[2] & div2[5] & !B2_dffs[5];
B2_dffs[2]_or_out = B2L71 # B2_dffs[2]_p0_out # B2_dffs[2]_p1_out # B2_dffs[2]_p2_out # B2_dffs[2]_p3_out # B2_dffs[2]_p4_out;
B2_dffs[2]_reg_input = B2_dffs[2]_or_out;
B2_dffs[2] = DFFE(B2_dffs[2]_reg_input, GLOBAL(CLK_IN), , , );


--A1L241 is reduce_nor~53 at LC112
A1L241_p0_out = div1[1] & !B1_dffs[1];
A1L241_p1_out = div1[3] & !B1_dffs[3];
A1L241_p2_out = div1[2] & B1_dffs[2];
A1L241_p3_out = !div1[2] & !B1_dffs[2];
A1L241_p4_out = !div1[1] & B1_dffs[1];
A1L241_or_out = A1L441 # A1L241_p0_out # A1L241_p1_out # A1L241_p2_out # A1L241_p3_out # A1L241_p4_out;
A1L241 = A1L241_or_out;