cpld_7064.vhd

CPLD的例子程序2,EPM7064芯片,PC104扩展卡上应用

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY cpld_7064 IS
  PORT ( 
         --============== ARM SINGALS ===================
         A                : IN      STD_LOGIC_VECTOR(5 DOWNTO 1);
  		 D                : INOUT   STD_LOGIC_VECTOR(10 DOWNTO 0);
         CS               : IN      STD_LOGIC;
		 WR               : IN      STD_LOGIC;
		 OE               : IN      STD_LOGIC;
		 LRST             : IN      STD_LOGIC;
		 CRST             : IN      STD_LOGIC;
		
		 --============== 429 SIGNSLS =====================
		 CS429            : IN      STD_LOGIC;
		 CLK_IN           : IN      STD_LOGIC;	
		 SEL              : OUT     STD_LOGIC;	
		 CARL             : IN      STD_LOGIC_VECTOR(3 DOWNTO 0);
         RDY              : IN      STD_LOGIC_VECTOR(7 DOWNTO 0);
         OE429            : OUT     STD_LOGIC_VECTOR(7 DOWNTO 0);
         LD429            : OUT     STD_LOGIC_VECTOR(11 DOWNTO 0);
         CLK4291          : OUT     STD_LOGIC;	
         CLK4292          : OUT     STD_LOGIC;	
		 IRQ              : OUT     STD_LOGIC;
		--=============== OTHER===========================
		 LCLK             : OUT     STD_LOGIC
		);									 
END ENTITY;

ARCHITECTURE BEHAVE OF cpld_7064 IS	   

SIGNAL REG_DATA                               : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL Divider1_set,Divider2_set,INT_REG_RD   : STD_LOGIC;
--SIGNAL IRQ_TEMP             : STD_LOGIC; 
signal clkcounter1          :std_logic_vector(5 downto 0)  ;
signal clkcounter2          :std_logic_vector(5 downto 0)  ;
signal 	IMREG      :   std_logic_vector(9 downto 0);
signal CARL_INT0,CARL_INT1,IMREG_SET  : STD_LOGIC; 

signal   div2              : Std_logic_Vector(5 downto 0);
signal   div1              : std_logic_vector(5 downto 0);
SIGNAL   clko1,clko2,rst       : STD_LOGIC; 
	
BEGIN

--rst  <=  LRST and CRST ;
rst  <=  CRST  ;

SEL  <=  A(1) ;

OE429   <=  "11111110" when CS429 = '0' and OE = '0' and A(5 DOWNTO 2) = "0000" else
            "11111101" when CS429 = '0' and OE = '0' and A(5 DOWNTO 2) = "0001" else
            "11111011" when CS429 = '0' and OE = '0' and A(5 DOWNTO 2) = "0010" else
            "11110111" when CS429 = '0' and OE = '0' and A(5 DOWNTO 2) = "0011" else
            "11101111" when CS429 = '0' and OE = '0' and A(5 DOWNTO 2) = "0100" else
            "11011111" when CS429 = '0' and OE = '0' and A(5 DOWNTO 2) = "0101" else
            "10111111" when CS429 = '0' and OE = '0' and A(5 DOWNTO 2) = "0110" else
            "01111111" when CS429 = '0' and OE = '0' and A(5 DOWNTO 2) = "0111" else
            "11111111";

LD429   <=  "111111111110" when CS429 = '0' and WR = '0' and A = "00000" else
            "111111111101" when CS429 = '0' and WR = '0' and A = "00010" else
            "111111111011" when CS429 = '0' and WR = '0' and A = "00100" else
            "111111110111" when CS429 = '0' and WR = '0' and A = "00110" else
            "111111101111" when CS429 = '0' and WR = '0' and A = "01000" else
            "111111011111" when CS429 = '0' and WR = '0' and A = "01010" else
            "111110111111" when CS429 = '0' and WR = '0' and A = "01100" else
            "111101111111" when CS429 = '0' and WR = '0' and A = "01110" else
            "111011111111" when CS429 = '0' and WR = '0' and A = "10000" else
            "110111111111" when CS429 = '0' and WR = '0' and A = "10010" else
            "101111111111" when CS429 = '0' and WR = '0' and A = "10100" else
            "011111111111" when CS429 = '0' and WR = '0' and A = "10110" else
            "111111111111";

	 
Divider1_set <= '1' when CS = '0' AND A(5 DOWNTO 1) = "00011" AND WR = '0' ELSE '0';
INT_REG_RD   <= '1' WHEN CS = '0' AND A(5 DOWNTO 1) = "00010" AND OE = '0' ELSE '0';
Divider2_set <= '1' when CS = '0' AND A(5 DOWNTO 1) = "00001" AND WR = '0' ELSE '0';
IMREG_SET <= '1'    when CS = '0' AND A(5 DOWNTO 1) = "00000" AND WR = '0' ELSE '0';

D <= '0' & REG_DATA                              WHEN  INT_REG_RD  = '1' ELSE
	 "ZZZZZZZZZZZ";	  

process(clk_IN,RST)
begin
    IF RST = '0' THEN
      div1  <= "010100";
	ELSif  clk_IN'event and clk_IN ='1' then
		if  Divider1_set = '1' then 
		div1 <= D(5 downto 0);		
	end if;
 end if;
end process;

process(clk_IN,RST)
begin
    IF RST = '0' THEN
      div2  <= "010100";
	elsif  clk_IN'event and clk_IN ='1' then
		if  Divider2_set = '1' then 
		div2 <= D(5 downto 0);		
	    end if;
	end if;
end process;

process(clk_IN)
begin
	if clk_IN'event and clk_IN = '1' then
		if clkcounter2 = div2 then
			clkcounter2  <= "000000";
		else
			clkcounter2 <= clkcounter2 + '1';
		end if;
	end if;
end process;



process(clk_IN)
begin	
   if clk_IN'event and clk_IN = '1' then
		if clkcounter2 = div2 then
			clko2 <= not clko2;
	     end if;
	end if;
end process;

process(clk_IN)
begin
  	if clk_IN'event and clk_IN = '1' then
		 if clkcounter1 = div1 then
			clkcounter1  <= "000000";
		else
			clkcounter1 <= clkcounter1 + '1';
		end if;
	end if;
end process;


process(clk_IN)
begin
    if clk_IN'event and clk_IN = '1' then
		if clkcounter1 = div1 then
			clko1 <= not clko1;
	    end if;
	end if;
end process;


CLK4292 <= clko2;

CLK4291 <= clko1;

process(clk_IN,RST)
begin
    IF RST = '0' THEN
        IMREG <=  "0000000000";
	elsif  clk_IN'event and clk_IN ='1' then
		if  IMREG_SET = '1' then 
		IMREG <= D(9 downto 0);		
	end if;
	end if;
end process;


process(RST ,CARL(0))
begin
	if  RST = '0' THEN
	   CARL_INT0 <= '0';
	ELSIF CARL(0)'event and CARL(0) ='1' then
	   CARL_INT0 <= '1';		
	end if;
end process;

process(RST ,CARL(1))
begin
	if  RST = '0' THEN
	   CARL_INT1 <= '0';
	ELSIF CARL(1)'event and CARL(1) ='1' then
	   CARL_INT1 <= '1';		
	end if;
end process;

REG_DATA <= ( not CARL_INT1 ) & ( not CARL_INT0 ) & RDY(7 downto 0) ;

	
IRQ <= NOT (   ( IMREG(9) AND CARL_INT1       )
            OR ( IMREG(8) AND CARL_INT0       )
            OR ( IMREG(7) AND (  NOT RDY(7) ) ) 
            OR ( IMREG(6) AND (  NOT RDY(6) ) ) 
            OR ( IMREG(5) AND (  NOT RDY(5) ) ) 
            OR ( IMREG(4) AND (  NOT RDY(4) ) ) 
            OR ( IMREG(3) AND (  NOT RDY(3) ) ) 
            OR ( IMREG(2) AND (  NOT RDY(2) ) ) 
            OR ( IMREG(1) AND (  NOT RDY(1) ) ) 
            OR ( IMREG(0) AND (  NOT RDY(0) ) ) 
           );
 
LCLK <= 'Z';
  
END BEHAVE;