cpld_lctl.map.eqn

CPLD的例子程序1,EPM7128芯片,ISA总线

B5L7_or_out = B5L7_p2_out # B5L7_p3_out # B5L7_p4_out;
B5L7 = B5L7 $ B5L7_or_out;


--B3L7 is lpm_latch:MD2_latch|q[6]~710
B3L7_p2_out = RST & !B3L7;
B3L7_p3_out = !B3L7 & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & MD[6];
B3L7_p4_out = !RST & B3L7 & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !MD[6];
B3L7_or_out = B3L7_p2_out # B3L7_p3_out # B3L7_p4_out;
B3L7 = B3L7 $ B3L7_or_out;


--B5L6 is lpm_latch:MD4_latch|q[5]~716
B5L6_p2_out = RST & !B5L6;
B5L6_p3_out = !B5L6 & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & MD[5];
B5L6_p4_out = !RST & B5L6 & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !MD[5];
B5L6_or_out = B5L6_p2_out # B5L6_p3_out # B5L6_p4_out;
B5L6 = B5L6 $ B5L6_or_out;


--B3L6 is lpm_latch:MD2_latch|q[5]~716
B3L6_p2_out = RST & !B3L6;
B3L6_p3_out = !B3L6 & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & MD[5];
B3L6_p4_out = !RST & B3L6 & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !MD[5];
B3L6_or_out = B3L6_p2_out # B3L6_p3_out # B3L6_p4_out;
B3L6 = B3L6 $ B3L6_or_out;


--B5L5 is lpm_latch:MD4_latch|q[4]~722
B5L5_p2_out = RST & !B5L5;
B5L5_p3_out = !B5L5 & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & MD[4];
B5L5_p4_out = !RST & B5L5 & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !MD[4];
B5L5_or_out = B5L5_p2_out # B5L5_p3_out # B5L5_p4_out;
B5L5 = B5L5 $ B5L5_or_out;


--B3L5 is lpm_latch:MD2_latch|q[4]~722
B3L5_p2_out = RST & !B3L5;
B3L5_p3_out = !B3L5 & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & MD[4];
B3L5_p4_out = !RST & B3L5 & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !MD[4];
B3L5_or_out = B3L5_p2_out # B3L5_p3_out # B3L5_p4_out;
B3L5 = B3L5 $ B3L5_or_out;


--B5L4 is lpm_latch:MD4_latch|q[3]~728
B5L4_p2_out = RST & !B5L4;
B5L4_p3_out = !B5L4 & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & MD[3];
B5L4_p4_out = !RST & B5L4 & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !MD[3];
B5L4_or_out = B5L4_p2_out # B5L4_p3_out # B5L4_p4_out;
B5L4 = B5L4 $ B5L4_or_out;


--B3L4 is lpm_latch:MD2_latch|q[3]~728
B3L4_p2_out = RST & !B3L4;
B3L4_p3_out = !B3L4 & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & MD[3];
B3L4_p4_out = !RST & B3L4 & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !MD[3];
B3L4_or_out = B3L4_p2_out # B3L4_p3_out # B3L4_p4_out;
B3L4 = B3L4 $ B3L4_or_out;


--B5L3 is lpm_latch:MD4_latch|q[2]~734
B5L3_p2_out = RST & !B5L3;
B5L3_p3_out = !B5L3 & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & MD[2];
B5L3_p4_out = !RST & B5L3 & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !MD[2];
B5L3_or_out = B5L3_p2_out # B5L3_p3_out # B5L3_p4_out;
B5L3 = B5L3 $ B5L3_or_out;


--B3L3 is lpm_latch:MD2_latch|q[2]~734
B3L3_p2_out = RST & !B3L3;
B3L3_p3_out = !B3L3 & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & MD[2];
B3L3_p4_out = !RST & B3L3 & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !MD[2];
B3L3_or_out = B3L3_p2_out # B3L3_p3_out # B3L3_p4_out;
B3L3 = B3L3 $ B3L3_or_out;


--B5L2 is lpm_latch:MD4_latch|q[1]~740
B5L2_p2_out = RST & !B5L2;
B5L2_p3_out = !B5L2 & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & MD[1];
B5L2_p4_out = !RST & B5L2 & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !MD[1];
B5L2_or_out = B5L2_p2_out # B5L2_p3_out # B5L2_p4_out;
B5L2 = B5L2 $ B5L2_or_out;


--B3L2 is lpm_latch:MD2_latch|q[1]~740
B3L2_p2_out = RST & !B3L2;
B3L2_p3_out = !B3L2 & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & MD[1];
B3L2_p4_out = !RST & B3L2 & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !MD[1];
B3L2_or_out = B3L2_p2_out # B3L2_p3_out # B3L2_p4_out;
B3L2 = B3L2 $ B3L2_or_out;


--B5L1 is lpm_latch:MD4_latch|q[0]~746
B5L1_p2_out = RST & !B5L1;
B5L1_p3_out = !B5L1 & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & MD[0];
B5L1_p4_out = !RST & B5L1 & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !MD[0];
B5L1_or_out = B5L1_p2_out # B5L1_p3_out # B5L1_p4_out;
B5L1 = B5L1 $ B5L1_or_out;


--B3L1 is lpm_latch:MD2_latch|q[0]~746
B3L1_p2_out = RST & !B3L1;
B3L1_p3_out = !B3L1 & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & MD[0];
B3L1_p4_out = !RST & B3L1 & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !MD[0];
B3L1_or_out = B3L1_p2_out # B3L1_p3_out # B3L1_p4_out;
B3L1 = B3L1 $ B3L1_or_out;


--B1L8 is lpm_latch:lpm_latch_DKO|q[7]~906
B1L8_p2_out = A1L84 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !B1L8;
B1L8_p3_out = !B1L8 & RST;
B1L8_p4_out = !A1L84 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & B1L8 & !RST;
B1L8_or_out = B1L8_p2_out # B1L8_p3_out # B1L8_p4_out;
B1L8 = B1L8 $ B1L8_or_out;


--B1L7 is lpm_latch:lpm_latch_DKO|q[6]~912
B1L7_p2_out = A1L64 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !B1L7;
B1L7_p3_out = !B1L7 & RST;
B1L7_p4_out = !A1L64 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & B1L7 & !RST;
B1L7_or_out = B1L7_p2_out # B1L7_p3_out # B1L7_p4_out;
B1L7 = B1L7 $ B1L7_or_out;


--B1L6 is lpm_latch:lpm_latch_DKO|q[5]~918
B1L6_p2_out = A1L44 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !B1L6;
B1L6_p3_out = !B1L6 & RST;
B1L6_p4_out = !A1L44 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & B1L6 & !RST;
B1L6_or_out = B1L6_p2_out # B1L6_p3_out # B1L6_p4_out;
B1L6 = B1L6 $ B1L6_or_out;


--B1L5 is lpm_latch:lpm_latch_DKO|q[4]~924
B1L5_p2_out = A1L24 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !B1L5;
B1L5_p3_out = !B1L5 & RST;
B1L5_p4_out = !A1L24 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & B1L5 & !RST;
B1L5_or_out = B1L5_p2_out # B1L5_p3_out # B1L5_p4_out;
B1L5 = B1L5 $ B1L5_or_out;


--B1L4 is lpm_latch:lpm_latch_DKO|q[3]~930
B1L4_p2_out = A1L04 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !B1L4;
B1L4_p3_out = !B1L4 & RST;
B1L4_p4_out = !A1L04 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & B1L4 & !RST;
B1L4_or_out = B1L4_p2_out # B1L4_p3_out # B1L4_p4_out;
B1L4 = B1L4 $ B1L4_or_out;


--B1L3 is lpm_latch:lpm_latch_DKO|q[2]~936
B1L3_p2_out = A1L83 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !B1L3;
B1L3_p3_out = !B1L3 & RST;
B1L3_p4_out = !A1L83 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & B1L3 & !RST;
B1L3_or_out = B1L3_p2_out # B1L3_p3_out # B1L3_p4_out;
B1L3 = B1L3 $ B1L3_or_out;


--B1L2 is lpm_latch:lpm_latch_DKO|q[1]~942
B1L2_p2_out = A1L63 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !B1L2;
B1L2_p3_out = !B1L2 & RST;
B1L2_p4_out = !A1L63 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & B1L2 & !RST;
B1L2_or_out = B1L2_p2_out # B1L2_p3_out # B1L2_p4_out;
B1L2 = B1L2 $ B1L2_or_out;


--B1L1 is lpm_latch:lpm_latch_DKO|q[0]~948
B1L1_p2_out = A1L43 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !B1L1;
B1L1_p3_out = !B1L1 & RST;
B1L1_p4_out = !A1L43 & !IOW & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & B1L1 & !RST;
B1L1_or_out = B1L1_p2_out # B1L1_p3_out # B1L1_p4_out;
B1L1 = B1L1 $ B1L1_or_out;


--A1L18 is D~11322
A1L18_p1_out = A1L521 & A1L76 & A1L86 & A1L96 & A1L07 & A1L17 & DK_IN[7];
A1L18_p2_out = INT_COM[7] & !A[8] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L18 = A1L18_p1_out # A1L18_p2_out;


--A1L28 is D~11325
A1L28_p1_out = A1L521 & DK_IN[6] & A1L76 & A1L86 & A1L96 & A1L07 & A1L17;
A1L28_p2_out = INT_COM[6] & !A[8] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L28 = A1L28_p1_out # A1L28_p2_out;


--A1L38 is D~11328
A1L38_p1_out = A1L521 & DK_IN[5] & A1L76 & A1L86 & A1L96 & A1L07 & A1L17;
A1L38_p2_out = INT_COM[5] & !A[8] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L38 = A1L38_p1_out # A1L38_p2_out;


--A1L48 is D~11331
A1L48_p1_out = A1L521 & DK_IN[4] & A1L76 & A1L86 & A1L96 & A1L07 & A1L17;
A1L48_p2_out = INT_COM[4] & !A[8] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L48 = A1L48_p1_out # A1L48_p2_out;


--A1L58 is D~11334
A1L58_p1_out = A1L521 & DK_IN[3] & A1L76 & A1L86 & A1L96 & A1L07 & A1L17;
A1L58_p2_out = INT_COM[3] & !A[8] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L58 = A1L58_p1_out # A1L58_p2_out;


--A1L68 is D~11337
A1L68_p1_out = A1L521 & DK_IN[2] & A1L76 & A1L86 & A1L96 & A1L07 & A1L17;
A1L68_p2_out = INT_COM[2] & !A[8] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L68 = A1L68_p1_out # A1L68_p2_out;


--A1L78 is D~11340
A1L78_p1_out = A1L521 & DK_IN[1] & A1L76 & A1L86 & A1L96 & A1L07 & A1L17;
A1L78_p2_out = INT_COM[1] & !A[8] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L78 = A1L78_p1_out # A1L78_p2_out;


--A1L88 is D~11343
A1L88_p1_out = A1L521 & DK_IN[0] & A1L76 & A1L86 & A1L96 & A1L07 & A1L17;
A1L88_p2_out = INT_COM[0] & !A[8] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L88 = A1L88_p1_out # A1L88_p2_out;


--A1L521 is RD_ISREG~25sexp
A1L521 = EXP(!A[8] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR);


--A1L76 is D~11257sexp
A1L76 = EXP(!A[2] & !A[1] & !A[0] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR);


--A1L86 is D~11259sexp
A1L86 = EXP(!A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR);


--A1L96 is D~11261sexp
A1L96 = EXP(!A[0] & A[1] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR);


--A1L07 is D~11263sexp
A1L07 = EXP(A[0] & A[1] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR);


--A1L17 is D~11265sexp
A1L17 = EXP(A[2] & !A[1] & !A[0] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR);


--RST is RST
--operation mode is input

RST = INPUT();


--A[11] is A[11]
--operation mode is input

A[11] = INPUT();


--A[10] is A[10]
--operation mode is input

A[10] = INPUT();


--A[9] is A[9]
--operation mode is input

A[9] = INPUT();


--A[8] is A[8]
--operation mode is input

A[8] = INPUT();


--A[7] is A[7]
--operation mode is input

A[7] = INPUT();


--A[6] is A[6]
--operation mode is input

A[6] = INPUT();


--A[5] is A[5]
--operation mode is input

A[5] = INPUT();


--A[4] is A[4]
--operation mode is input

A[4] = INPUT();


--A[3] is A[3]
--operation mode is input

A[3] = INPUT();


--A[2] is A[2]
--operation mode is input

A[2] = INPUT();


--A[1] is A[1]
--operation mode is input

A[1] = INPUT();


--A[0] is A[0]
--operation mode is input

A[0] = INPUT();


--AEN is AEN
--operation mode is input

AEN = INPUT();


--IOW is IOW
--operation mode is input

IOW = INPUT();


--IOR is IOR
--operation mode is input

IOR = INPUT();


--MCS is MCS
--operation mode is input

MCS = INPUT();


--MWR is MWR
--operation mode is input

MWR = INPUT();


--MD[7] is MD[7]
--operation mode is input

MD[7] = INPUT();


--MD[6] is MD[6]
--operation mode is input

MD[6] = INPUT();


--MD[5] is MD[5]
--operation mode is input

MD[5] = INPUT();


--MD[4] is MD[4]
--operation mode is input