📄 cpld_lctl.map.eqn
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--A1L27 is D~11274
A1L27_p0_out = B3L8 & A1L521 & A1L76 & !A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L27_p1_out = A1L521 & !A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & B2L8;
A1L27_p2_out = B6L8 & A1L521 & A1L76 & !A[1] & !A[0] & A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96 & A1L07;
A1L27_p3_out = B5L8 & A1L521 & A1L76 & A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96;
A1L27_p4_out = B4L8 & A1L521 & A1L76 & A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86;
A1L27_or_out = A1L18 # A1L27_p0_out # A1L27_p1_out # A1L27_p2_out # A1L27_p3_out # A1L27_p4_out;
A1L27 = A1L27_or_out;
--A1L37 is D~11279
A1L37_p1_out = !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[8] & !A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !IOR;
A1L37_p2_out = !AEN & !A[11] & !A[10] & A[9] & !A[6] & A[8] & !A[4] & !A[5] & A[7] & !A[2] & !IOR;
A1L37_p3_out = !AEN & !A[11] & !A[10] & A[9] & !A[6] & A[8] & !A[4] & !A[5] & A[7] & !A[1] & !A[0] & !IOR;
A1L37_p4_out = !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4] & A[5] & !A[7] & !A[3] & !A[2] & !A[1] & !A[0] & !IOR;
A1L37_or_out = A1L37_p1_out # A1L37_p2_out # A1L37_p3_out # A1L37_p4_out;
A1L37 = A1L37_or_out;
--A1L47 is D~11285
A1L47_p0_out = B3L7 & A1L521 & A1L76 & !A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L47_p1_out = A1L521 & !A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & B2L7;
A1L47_p2_out = B6L7 & A1L521 & A1L76 & !A[1] & !A[0] & A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96 & A1L07;
A1L47_p3_out = B5L7 & A1L521 & A1L76 & A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96;
A1L47_p4_out = B4L7 & A1L521 & A1L76 & A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86;
A1L47_or_out = A1L28 # A1L47_p0_out # A1L47_p1_out # A1L47_p2_out # A1L47_p3_out # A1L47_p4_out;
A1L47 = A1L47_or_out;
--A1L57 is D~11291
A1L57_p0_out = B3L6 & A1L521 & A1L76 & !A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L57_p1_out = A1L521 & !A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & B2L6;
A1L57_p2_out = B6L6 & A1L521 & A1L76 & !A[1] & !A[0] & A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96 & A1L07;
A1L57_p3_out = B5L6 & A1L521 & A1L76 & A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96;
A1L57_p4_out = B4L6 & A1L521 & A1L76 & A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86;
A1L57_or_out = A1L38 # A1L57_p0_out # A1L57_p1_out # A1L57_p2_out # A1L57_p3_out # A1L57_p4_out;
A1L57 = A1L57_or_out;
--A1L67 is D~11297
A1L67_p0_out = B3L5 & A1L521 & A1L76 & !A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L67_p1_out = A1L521 & !A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & B2L5;
A1L67_p2_out = B6L5 & A1L521 & A1L76 & !A[1] & !A[0] & A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96 & A1L07;
A1L67_p3_out = B5L5 & A1L521 & A1L76 & A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96;
A1L67_p4_out = B4L5 & A1L521 & A1L76 & A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86;
A1L67_or_out = A1L48 # A1L67_p0_out # A1L67_p1_out # A1L67_p2_out # A1L67_p3_out # A1L67_p4_out;
A1L67 = A1L67_or_out;
--A1L77 is D~11303
A1L77_p0_out = B3L4 & A1L521 & A1L76 & !A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L77_p1_out = A1L521 & !A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & B2L4;
A1L77_p2_out = B6L4 & A1L521 & A1L76 & !A[1] & !A[0] & A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96 & A1L07;
A1L77_p3_out = B5L4 & A1L521 & A1L76 & A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96;
A1L77_p4_out = B4L4 & A1L521 & A1L76 & A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86;
A1L77_or_out = A1L58 # A1L77_p0_out # A1L77_p1_out # A1L77_p2_out # A1L77_p3_out # A1L77_p4_out;
A1L77 = A1L77_or_out;
--A1L87 is D~11309
A1L87_p0_out = B3L3 & A1L521 & A1L76 & !A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L87_p1_out = A1L521 & !A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & B2L3;
A1L87_p2_out = B6L3 & A1L521 & A1L76 & !A[1] & !A[0] & A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96 & A1L07;
A1L87_p3_out = B5L3 & A1L521 & A1L76 & A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96;
A1L87_p4_out = B4L3 & A1L521 & A1L76 & A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86;
A1L87_or_out = A1L68 # A1L87_p0_out # A1L87_p1_out # A1L87_p2_out # A1L87_p3_out # A1L87_p4_out;
A1L87 = A1L87_or_out;
--A1L97 is D~11315
A1L97_p0_out = B3L2 & A1L521 & A1L76 & !A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L97_p1_out = A1L521 & !A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & B2L2;
A1L97_p2_out = B6L2 & A1L521 & A1L76 & !A[1] & !A[0] & A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96 & A1L07;
A1L97_p3_out = B5L2 & A1L521 & A1L76 & A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96;
A1L97_p4_out = B4L2 & A1L521 & A1L76 & A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86;
A1L97_or_out = A1L78 # A1L97_p0_out # A1L97_p1_out # A1L97_p2_out # A1L97_p3_out # A1L97_p4_out;
A1L97 = A1L97_or_out;
--A1L08 is D~11321
A1L08_p0_out = B3L1 & A1L521 & A1L76 & !A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR;
A1L08_p1_out = A1L521 & !A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & B2L1;
A1L08_p2_out = B6L1 & A1L521 & A1L76 & !A[1] & !A[0] & A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96 & A1L07;
A1L08_p3_out = B5L1 & A1L521 & A1L76 & A[1] & A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86 & A1L96;
A1L08_p4_out = B4L1 & A1L521 & A1L76 & A[1] & !A[0] & !A[2] & A[7] & !A[5] & A[8] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !IOR & A1L86;
A1L08_or_out = A1L88 # A1L08_p0_out # A1L08_p1_out # A1L08_p2_out # A1L08_p3_out # A1L08_p4_out;
A1L08 = A1L08_or_out;
--A1L101 is IRQ1~59
A1L101_p1_out = INT_COM[3] & INT_COM[2] & INT_COM[1] & INT_COM[0];
A1L101_or_out = A1L101_p1_out;
A1L101 = A1L101_or_out;
--A1L301 is IRQ2~11
A1L301_p1_out = INT_COM[7] & INT_COM[6] & INT_COM[5] & INT_COM[4];
A1L301_or_out = A1L301_p1_out;
A1L301 = A1L301_or_out;
--A1L601 is IRQ4~11
A1L601_p1_out = DK_IN[3] & DK_IN[2] & DK_IN[1] & DK_IN[0];
A1L601_or_out = A1L601_p1_out;
A1L601 = A1L601_or_out;
--A1L421 is PPS~2
A1L421_or_out = PPS;
A1L421 = A1L421_or_out;
--A1L42 is CS_PA~18
A1L42_p1_out = A[5] & A[7] & A[3] & !AEN & !A[11] & !A[10] & A[9] & A[6] & A[8] & A[4];
A1L42_or_out = A1L42_p1_out;
A1L42 = !(A1L42_or_out);
--A1L62 is CS_PC~12
A1L62_p1_out = A[8] & !A[4] & A[5] & A[7] & A[3] & !AEN & !A[11] & !A[10] & A[9] & A[6];
A1L62_or_out = A1L62_p1_out;
A1L62 = !(A1L62_or_out);
--A1L03 is CS_PG~10
A1L03_p1_out = A[7] & A[3] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4] & !A[5] & A[8];
A1L03_or_out = A1L03_p1_out;
A1L03 = !(A1L03_or_out);
--A1L13 is CS_PH~10
A1L13_p1_out = !A[5] & !A[8] & A[7] & A[3] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4];
A1L13_or_out = A1L13_p1_out;
A1L13 = !(A1L13_or_out);
--A1L52 is CS_PB~12
A1L52_p1_out = A[4] & !A[8] & A[5] & A[7] & A[3] & !AEN & !A[11] & !A[10] & A[9] & A[6];
A1L52_or_out = A1L52_p1_out;
A1L52 = !(A1L52_or_out);
--A1L72 is CS_PD~10
A1L72_p1_out = !A[4] & !A[8] & A[5] & A[7] & A[3] & !AEN & !A[11] & !A[10] & A[9] & A[6];
A1L72_or_out = A1L72_p1_out;
A1L72 = !(A1L72_or_out);
--A1L82 is CS_PE~16
A1L82_p1_out = A[8] & A[5] & A[7] & A[3] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4];
A1L82_or_out = A1L82_p1_out;
A1L82 = !(A1L82_or_out);
--A1L92 is CS_PF~10
A1L92_p1_out = !A[8] & A[5] & A[7] & A[3] & !AEN & !A[11] & !A[10] & A[9] & !A[6] & !A[4];
A1L92_or_out = A1L92_p1_out;
A1L92 = !(A1L92_or_out);
--B6L8 is lpm_latch:MD5_latch|q[7]~704
B6L8_p2_out = MD[7] & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !B6L8;
B6L8_p3_out = !B6L8 & RST;
B6L8_p4_out = !MD[7] & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & B6L8 & !RST;
B6L8_or_out = B6L8_p2_out # B6L8_p3_out # B6L8_p4_out;
B6L8 = B6L8 $ B6L8_or_out;
--B6L7 is lpm_latch:MD5_latch|q[6]~710
B6L7_p2_out = RST & !B6L7;
B6L7_p3_out = !B6L7 & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & MD[6];
B6L7_p4_out = !RST & B6L7 & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !MD[6];
B6L7_or_out = B6L7_p2_out # B6L7_p3_out # B6L7_p4_out;
B6L7 = B6L7 $ B6L7_or_out;
--B6L6 is lpm_latch:MD5_latch|q[5]~716
B6L6_p2_out = RST & !B6L6;
B6L6_p3_out = !B6L6 & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & MD[5];
B6L6_p4_out = !RST & B6L6 & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !MD[5];
B6L6_or_out = B6L6_p2_out # B6L6_p3_out # B6L6_p4_out;
B6L6 = B6L6 $ B6L6_or_out;
--B6L5 is lpm_latch:MD5_latch|q[4]~722
B6L5_p2_out = RST & !B6L5;
B6L5_p3_out = !B6L5 & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & MD[4];
B6L5_p4_out = !RST & B6L5 & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !MD[4];
B6L5_or_out = B6L5_p2_out # B6L5_p3_out # B6L5_p4_out;
B6L5 = B6L5 $ B6L5_or_out;
--B6L4 is lpm_latch:MD5_latch|q[3]~728
B6L4_p2_out = RST & !B6L4;
B6L4_p3_out = !B6L4 & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & MD[3];
B6L4_p4_out = !RST & B6L4 & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !MD[3];
B6L4_or_out = B6L4_p2_out # B6L4_p3_out # B6L4_p4_out;
B6L4 = B6L4 $ B6L4_or_out;
--B6L3 is lpm_latch:MD5_latch|q[2]~734
B6L3_p2_out = RST & !B6L3;
B6L3_p3_out = !B6L3 & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & MD[2];
B6L3_p4_out = !RST & B6L3 & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !MD[2];
B6L3_or_out = B6L3_p2_out # B6L3_p3_out # B6L3_p4_out;
B6L3 = B6L3 $ B6L3_or_out;
--B6L2 is lpm_latch:MD5_latch|q[1]~740
B6L2_p2_out = RST & !B6L2;
B6L2_p3_out = !B6L2 & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & MD[1];
B6L2_p4_out = !RST & B6L2 & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !MD[1];
B6L2_or_out = B6L2_p2_out # B6L2_p3_out # B6L2_p4_out;
B6L2 = B6L2 $ B6L2_or_out;
--B6L1 is lpm_latch:MD5_latch|q[0]~746
B6L1_p2_out = RST & !B6L1;
B6L1_p3_out = !B6L1 & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & MD[0];
B6L1_p4_out = !RST & B6L1 & MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !MD[0];
B6L1_or_out = B6L1_p2_out # B6L1_p3_out # B6L1_p4_out;
B6L1 = B6L1 $ B6L1_or_out;
--B4L8 is lpm_latch:MD3_latch|q[7]~704
B4L8_p2_out = MD[7] & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & !B4L8;
B4L8_p3_out = !B4L8 & RST;
B4L8_p4_out = !MD[7] & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & B4L8 & !RST;
B4L8_or_out = B4L8_p2_out # B4L8_p3_out # B4L8_p4_out;
B4L8 = B4L8 $ B4L8_or_out;
--B2L8 is lpm_latch:MD1_latch|q[7]~704
B2L8_p2_out = MD[7] & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !B2L8;
B2L8_p3_out = !B2L8 & RST;
B2L8_p4_out = !MD[7] & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & B2L8 & !RST;
B2L8_or_out = B2L8_p2_out # B2L8_p3_out # B2L8_p4_out;
B2L8 = B2L8 $ B2L8_or_out;
--B4L7 is lpm_latch:MD3_latch|q[6]~710
B4L7_p2_out = RST & !B4L7;
B4L7_p3_out = !B4L7 & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & MD[6];
B4L7_p4_out = !RST & B4L7 & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & !MD[6];
B4L7_or_out = B4L7_p2_out # B4L7_p3_out # B4L7_p4_out;
B4L7 = B4L7 $ B4L7_or_out;
--B2L7 is lpm_latch:MD1_latch|q[6]~710
B2L7_p2_out = RST & !B2L7;
B2L7_p3_out = !B2L7 & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & MD[6];
B2L7_p4_out = !RST & B2L7 & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !MD[6];
B2L7_or_out = B2L7_p2_out # B2L7_p3_out # B2L7_p4_out;
B2L7 = B2L7 $ B2L7_or_out;
--B4L6 is lpm_latch:MD3_latch|q[5]~716
B4L6_p2_out = RST & !B4L6;
B4L6_p3_out = !B4L6 & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & MD[5];
B4L6_p4_out = !RST & B4L6 & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & !MD[5];
B4L6_or_out = B4L6_p2_out # B4L6_p3_out # B4L6_p4_out;
B4L6 = B4L6 $ B4L6_or_out;
--B2L6 is lpm_latch:MD1_latch|q[5]~716
B2L6_p2_out = RST & !B2L6;
B2L6_p3_out = !B2L6 & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & MD[5];
B2L6_p4_out = !RST & B2L6 & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !MD[5];
B2L6_or_out = B2L6_p2_out # B2L6_p3_out # B2L6_p4_out;
B2L6 = B2L6 $ B2L6_or_out;
--B4L5 is lpm_latch:MD3_latch|q[4]~722
B4L5_p2_out = RST & !B4L5;
B4L5_p3_out = !B4L5 & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & MD[4];
B4L5_p4_out = !RST & B4L5 & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & !MD[4];
B4L5_or_out = B4L5_p2_out # B4L5_p3_out # B4L5_p4_out;
B4L5 = B4L5 $ B4L5_or_out;
--B2L5 is lpm_latch:MD1_latch|q[4]~722
B2L5_p2_out = RST & !B2L5;
B2L5_p3_out = !B2L5 & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & MD[4];
B2L5_p4_out = !RST & B2L5 & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !MD[4];
B2L5_or_out = B2L5_p2_out # B2L5_p3_out # B2L5_p4_out;
B2L5 = B2L5 $ B2L5_or_out;
--B4L4 is lpm_latch:MD3_latch|q[3]~728
B4L4_p2_out = RST & !B4L4;
B4L4_p3_out = !B4L4 & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & MD[3];
B4L4_p4_out = !RST & B4L4 & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & !MD[3];
B4L4_or_out = B4L4_p2_out # B4L4_p3_out # B4L4_p4_out;
B4L4 = B4L4 $ B4L4_or_out;
--B2L4 is lpm_latch:MD1_latch|q[3]~728
B2L4_p2_out = RST & !B2L4;
B2L4_p3_out = !B2L4 & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & MD[3];
B2L4_p4_out = !RST & B2L4 & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !MD[3];
B2L4_or_out = B2L4_p2_out # B2L4_p3_out # B2L4_p4_out;
B2L4 = B2L4 $ B2L4_or_out;
--B4L3 is lpm_latch:MD3_latch|q[2]~734
B4L3_p2_out = RST & !B4L3;
B4L3_p3_out = !B4L3 & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & MD[2];
B4L3_p4_out = !RST & B4L3 & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & !MD[2];
B4L3_or_out = B4L3_p2_out # B4L3_p3_out # B4L3_p4_out;
B4L3 = B4L3 $ B4L3_or_out;
--B2L3 is lpm_latch:MD1_latch|q[2]~734
B2L3_p2_out = RST & !B2L3;
B2L3_p3_out = !B2L3 & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & MD[2];
B2L3_p4_out = !RST & B2L3 & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !MD[2];
B2L3_or_out = B2L3_p2_out # B2L3_p3_out # B2L3_p4_out;
B2L3 = B2L3 $ B2L3_or_out;
--B4L2 is lpm_latch:MD3_latch|q[1]~740
B4L2_p2_out = RST & !B4L2;
B4L2_p3_out = !B4L2 & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & MD[1];
B4L2_p4_out = !RST & B4L2 & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & !MD[1];
B4L2_or_out = B4L2_p2_out # B4L2_p3_out # B4L2_p4_out;
B4L2 = B4L2 $ B4L2_or_out;
--B2L2 is lpm_latch:MD1_latch|q[1]~740
B2L2_p2_out = RST & !B2L2;
B2L2_p3_out = !B2L2 & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & MD[1];
B2L2_p4_out = !RST & B2L2 & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !MD[1];
B2L2_or_out = B2L2_p2_out # B2L2_p3_out # B2L2_p4_out;
B2L2 = B2L2 $ B2L2_or_out;
--B4L1 is lpm_latch:MD3_latch|q[0]~746
B4L1_p2_out = RST & !B4L1;
B4L1_p3_out = !B4L1 & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & MD[0];
B4L1_p4_out = !RST & B4L1 & !MA[2] & !MA[3] & !MCS & !MWR & MA[1] & !MA[0] & !MD[0];
B4L1_or_out = B4L1_p2_out # B4L1_p3_out # B4L1_p4_out;
B4L1 = B4L1 $ B4L1_or_out;
--B2L1 is lpm_latch:MD1_latch|q[0]~746
B2L1_p2_out = RST & !B2L1;
B2L1_p3_out = !B2L1 & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & MD[0];
B2L1_p4_out = !RST & B2L1 & !MA[2] & !MA[3] & !MCS & !MWR & !MA[1] & !MA[0] & !MD[0];
B2L1_or_out = B2L1_p2_out # B2L1_p3_out # B2L1_p4_out;
B2L1 = B2L1 $ B2L1_or_out;
--B5L8 is lpm_latch:MD4_latch|q[7]~704
B5L8_p2_out = MD[7] & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !B5L8;
B5L8_p3_out = !B5L8 & RST;
B5L8_p4_out = !MD[7] & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & B5L8 & !RST;
B5L8_or_out = B5L8_p2_out # B5L8_p3_out # B5L8_p4_out;
B5L8 = B5L8 $ B5L8_or_out;
--B3L8 is lpm_latch:MD2_latch|q[7]~704
B3L8_p2_out = MD[7] & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !B3L8;
B3L8_p3_out = !B3L8 & RST;
B3L8_p4_out = !MD[7] & !MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & B3L8 & !RST;
B3L8_or_out = B3L8_p2_out # B3L8_p3_out # B3L8_p4_out;
B3L8 = B3L8 $ B3L8_or_out;
--B5L7 is lpm_latch:MD4_latch|q[6]~710
B5L7_p2_out = RST & !B5L7;
B5L7_p3_out = !B5L7 & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & MD[6];
B5L7_p4_out = !RST & B5L7 & MA[1] & !MA[2] & !MA[3] & !MCS & !MWR & MA[0] & !MD[6];
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