cpld_lctl.hier_info

CPLD的例子程序1,EPM7128芯片,ISA总线

|CPLD_LCTL
RST => lpm_latch:lpm_latch_DKO.aset
RST => lpm_latch:MD5_latch.aset
RST => lpm_latch:MD4_latch.aset
RST => lpm_latch:MD3_latch.aset
RST => lpm_latch:MD2_latch.aset
RST => lpm_latch:MD1_latch.aset
A[0] => reduce_nor~6.IN1
A[0] => equal~9.IN0
A[0] => reduce_nor~8.IN1
A[0] => reduce_nor~10.IN2
A[0] => reduce_nor~12.IN2
A[0] => reduce_nor~22.IN1
A[1] => reduce_nor~6.IN0
A[1] => equal~10.IN0
A[1] => reduce_nor~9.IN1
A[1] => reduce_nor~10.IN1
A[1] => reduce_nor~12.IN1
A[1] => reduce_nor~22.IN0
A[2] => equal~8.IN0
A[2] => reduce_nor~7.IN0
A[2] => reduce_nor~8.IN0
A[2] => reduce_nor~9.IN0
A[2] => reduce_nor~10.IN0
A[2] => reduce_nor~12.IN0
A[2] => reduce_nor~21.IN7
A[3] => reduce_nor~11.IN3
A[3] => equal~13.IN0
A[3] => reduce_nor~21.IN6
A[4] => reduce_nor~0.IN4
A[4] => equal~11.IN0
A[4] => reduce_nor~15.IN2
A[4] => reduce_nor~16.IN3
A[4] => reduce_nor~17.IN3
A[4] => reduce_nor~18.IN4
A[4] => reduce_nor~19.IN4
A[4] => reduce_nor~20.IN5
A[4] => reduce_nor~21.IN5
A[5] => reduce_nor~0.IN3
A[5] => reduce_nor~19.IN3
A[5] => reduce_nor~20.IN4
A[5] => equal~14.IN0
A[6] => reduce_nor~0.IN2
A[6] => equal~12.IN0
A[6] => reduce_nor~17.IN2
A[6] => reduce_nor~18.IN3
A[6] => reduce_nor~19.IN2
A[6] => reduce_nor~20.IN3
A[6] => reduce_nor~21.IN4
A[7] => equal~0.IN0
A[7] => reduce_nor~11.IN2
A[7] => reduce_nor~21.IN3
A[8] => equal~1.IN0
A[8] => reduce_nor~14.IN2
A[8] => reduce_nor~16.IN2
A[8] => reduce_nor~18.IN2
A[8] => reduce_nor~20.IN2
A[8] => reduce_nor~21.IN2
A[9] => equal~2.IN0
A[10] => reduce_nor~0.IN1
A[10] => reduce_nor~11.IN1
A[10] => reduce_nor~13.IN1
A[10] => reduce_nor~14.IN1
A[10] => reduce_nor~15.IN1
A[10] => reduce_nor~16.IN1
A[10] => reduce_nor~17.IN1
A[10] => reduce_nor~18.IN1
A[10] => reduce_nor~19.IN1
A[10] => reduce_nor~20.IN1
A[10] => reduce_nor~21.IN1
A[11] => reduce_nor~0.IN0
A[11] => reduce_nor~11.IN0
A[11] => reduce_nor~13.IN0
A[11] => reduce_nor~14.IN0
A[11] => reduce_nor~15.IN0
A[11] => reduce_nor~16.IN0
A[11] => reduce_nor~17.IN0
A[11] => reduce_nor~18.IN0
A[11] => reduce_nor~19.IN0
A[11] => reduce_nor~20.IN0
A[11] => reduce_nor~21.IN0
D[0] <= D~77
D[1] <= D~70
D[2] <= D~63
D[3] <= D~56
D[4] <= D~49
D[5] <= D~42
D[6] <= D~35
D[7] <= D~28
AEN => CS_GPS~0.IN0
IOW => DKWR~1.IN0
IOR => D~9.IN0
IRQ1 <= IRQ1~2.DB_MAX_OUTPUT_PORT_TYPE
IRQ2 <= IRQ2~2.DB_MAX_OUTPUT_PORT_TYPE
IRQ3 <= PPS.DB_MAX_OUTPUT_PORT_TYPE
IRQ4 <= IRQ4~2.DB_MAX_OUTPUT_PORT_TYPE
MCS => WR_MD1~0.IN0
MCS => WR_MD2~0.IN0
MCS => WR_MD3~0.IN0
MCS => WR_MD4~0.IN0
MCS => WR_MD5~0.IN0
MWR => WR_MD1~1.IN0
MWR => WR_MD2~1.IN0
MWR => WR_MD3~1.IN0
MWR => WR_MD4~1.IN0
MWR => WR_MD5~1.IN0
MD[0] => lpm_latch:MD5_latch.data[0]
MD[0] => lpm_latch:MD4_latch.data[0]
MD[0] => lpm_latch:MD3_latch.data[0]
MD[0] => lpm_latch:MD2_latch.data[0]
MD[0] => lpm_latch:MD1_latch.data[0]
MD[1] => lpm_latch:MD5_latch.data[1]
MD[1] => lpm_latch:MD4_latch.data[1]
MD[1] => lpm_latch:MD3_latch.data[1]
MD[1] => lpm_latch:MD2_latch.data[1]
MD[1] => lpm_latch:MD1_latch.data[1]
MD[2] => lpm_latch:MD5_latch.data[2]
MD[2] => lpm_latch:MD4_latch.data[2]
MD[2] => lpm_latch:MD3_latch.data[2]
MD[2] => lpm_latch:MD2_latch.data[2]
MD[2] => lpm_latch:MD1_latch.data[2]
MD[3] => lpm_latch:MD5_latch.data[3]
MD[3] => lpm_latch:MD4_latch.data[3]
MD[3] => lpm_latch:MD3_latch.data[3]
MD[3] => lpm_latch:MD2_latch.data[3]
MD[3] => lpm_latch:MD1_latch.data[3]
MD[4] => lpm_latch:MD5_latch.data[4]
MD[4] => lpm_latch:MD4_latch.data[4]
MD[4] => lpm_latch:MD3_latch.data[4]
MD[4] => lpm_latch:MD2_latch.data[4]
MD[4] => lpm_latch:MD1_latch.data[4]
MD[5] => lpm_latch:MD5_latch.data[5]
MD[5] => lpm_latch:MD4_latch.data[5]
MD[5] => lpm_latch:MD3_latch.data[5]
MD[5] => lpm_latch:MD2_latch.data[5]
MD[5] => lpm_latch:MD1_latch.data[5]
MD[6] => lpm_latch:MD5_latch.data[6]
MD[6] => lpm_latch:MD4_latch.data[6]
MD[6] => lpm_latch:MD3_latch.data[6]
MD[6] => lpm_latch:MD2_latch.data[6]
MD[6] => lpm_latch:MD1_latch.data[6]
MD[7] => lpm_latch:MD5_latch.data[7]
MD[7] => lpm_latch:MD4_latch.data[7]
MD[7] => lpm_latch:MD3_latch.data[7]
MD[7] => lpm_latch:MD2_latch.data[7]
MD[7] => lpm_latch:MD1_latch.data[7]
MA[0] => reduce_nor~1.IN3
MA[0] => equal~3.IN0
MA[0] => reduce_nor~3.IN2
MA[0] => equal~5.IN0
MA[0] => reduce_nor~5.IN2
MA[1] => reduce_nor~1.IN2
MA[1] => reduce_nor~2.IN2
MA[1] => equal~4.IN0
MA[1] => equal~6.IN0
MA[1] => reduce_nor~5.IN1
MA[2] => reduce_nor~1.IN1
MA[2] => reduce_nor~2.IN1
MA[2] => reduce_nor~3.IN1
MA[2] => reduce_nor~4.IN1
MA[2] => equal~7.IN0
MA[3] => reduce_nor~1.IN0
MA[3] => reduce_nor~2.IN0
MA[3] => reduce_nor~3.IN0
MA[3] => reduce_nor~4.IN0
MA[3] => reduce_nor~5.IN0
PPS => IRQ3.DATAIN
DK_IN[0] => D~71.DATAA
DK_IN[0] => IRQ4~2.IN0
DK_IN[1] => D~64.DATAA
DK_IN[1] => IRQ4~1.IN0
DK_IN[2] => D~57.DATAA
DK_IN[2] => IRQ4~0.IN1
DK_IN[3] => D~50.DATAA
DK_IN[3] => IRQ4~0.IN0
DK_IN[4] => D~43.DATAA
DK_IN[5] => D~36.DATAA
DK_IN[6] => D~29.DATAA
DK_IN[7] => D~16.DATAA
DK_OUT[0] <= lpm_latch:lpm_latch_DKO.q[0]
DK_OUT[1] <= lpm_latch:lpm_latch_DKO.q[1]
DK_OUT[2] <= lpm_latch:lpm_latch_DKO.q[2]
DK_OUT[3] <= lpm_latch:lpm_latch_DKO.q[3]
DK_OUT[4] <= lpm_latch:lpm_latch_DKO.q[4]
DK_OUT[5] <= lpm_latch:lpm_latch_DKO.q[5]
DK_OUT[6] <= lpm_latch:lpm_latch_DKO.q[6]
DK_OUT[7] <= lpm_latch:lpm_latch_DKO.q[7]
INT_COM[0] => D~76.DATAB
INT_COM[0] => IRQ1~2.IN0
INT_COM[1] => D~69.DATAB
INT_COM[1] => IRQ1~1.IN0
INT_COM[2] => D~62.DATAB
INT_COM[2] => IRQ1~0.IN1
INT_COM[3] => D~55.DATAB
INT_COM[3] => IRQ1~0.IN0
INT_COM[4] => D~48.DATAB
INT_COM[4] => IRQ2~2.IN0
INT_COM[5] => D~41.DATAB
INT_COM[5] => IRQ2~1.IN0
INT_COM[6] => D~34.DATAB
INT_COM[6] => IRQ2~0.IN1
INT_COM[7] => D~26.DATAB
INT_COM[7] => IRQ2~0.IN0
CS_COM[0] <= CS_PA~1.DB_MAX_OUTPUT_PORT_TYPE
CS_COM[1] <= CS_PB~1.DB_MAX_OUTPUT_PORT_TYPE
CS_COM[2] <= CS_PC~1.DB_MAX_OUTPUT_PORT_TYPE
CS_COM[3] <= CS_PD~1.DB_MAX_OUTPUT_PORT_TYPE
CS_COM[4] <= CS_PE~1.DB_MAX_OUTPUT_PORT_TYPE
CS_COM[5] <= CS_PF~1.DB_MAX_OUTPUT_PORT_TYPE
CS_COM[6] <= CS_PG~1.DB_MAX_OUTPUT_PORT_TYPE
CS_COM[7] <= CS_PH~1.DB_MAX_OUTPUT_PORT_TYPE


|CPLD_LCTL|lpm_latch:MD1_latch
aclr => prn[7].IN0
aclr => prn[6].IN0
aclr => prn[5].IN0
aclr => prn[4].IN0
aclr => prn[3].IN0
aclr => prn[2].IN0
aclr => prn[1].IN0
aclr => prn[0].IN0
aconst => ~NO_FANOUT~


|CPLD_LCTL|lpm_latch:MD2_latch
aclr => prn[7].IN0
aclr => prn[6].IN0
aclr => prn[5].IN0
aclr => prn[4].IN0
aclr => prn[3].IN0
aclr => prn[2].IN0
aclr => prn[1].IN0
aclr => prn[0].IN0
aconst => ~NO_FANOUT~


|CPLD_LCTL|lpm_latch:MD3_latch
aclr => prn[7].IN0
aclr => prn[6].IN0
aclr => prn[5].IN0
aclr => prn[4].IN0
aclr => prn[3].IN0
aclr => prn[2].IN0
aclr => prn[1].IN0
aclr => prn[0].IN0
aconst => ~NO_FANOUT~


|CPLD_LCTL|lpm_latch:MD4_latch
aclr => prn[7].IN0
aclr => prn[6].IN0
aclr => prn[5].IN0
aclr => prn[4].IN0
aclr => prn[3].IN0
aclr => prn[2].IN0
aclr => prn[1].IN0
aclr => prn[0].IN0
aconst => ~NO_FANOUT~


|CPLD_LCTL|lpm_latch:MD5_latch
aclr => prn[7].IN0
aclr => prn[6].IN0
aclr => prn[5].IN0
aclr => prn[4].IN0
aclr => prn[3].IN0
aclr => prn[2].IN0
aclr => prn[1].IN0
aclr => prn[0].IN0
aconst => ~NO_FANOUT~


|CPLD_LCTL|lpm_latch:lpm_latch_DKO
aclr => prn[7].IN0
aclr => prn[6].IN0
aclr => prn[5].IN0
aclr => prn[4].IN0
aclr => prn[3].IN0
aclr => prn[2].IN0
aclr => prn[1].IN0
aclr => prn[0].IN0
aconst => ~NO_FANOUT~