cpld_lctl.map.qmsg

CPLD的例子程序1,EPM7128芯片,ISA总线

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 14 15:09:28 2007 " "Info: Processing started: Fri Sep 14 15:09:28 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off CPLD_LCTL -c CPLD_LCTL " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off CPLD_LCTL -c CPLD_LCTL" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CPLD_LCTL.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CPLD_LCTL.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CPLD_LCTL-BEHAVE " "Info: Found design unit 1: CPLD_LCTL-BEHAVE" {  } { { "CPLD_LCTL.vhd" "" { Text "E:/Communication Maneger/CPLD/LCTL_1.2/CPLD_LCTL.vhd" 39 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 CPLD_LCTL " "Info: Found entity 1: CPLD_LCTL" {  } { { "CPLD_LCTL.vhd" "" { Text "E:/Communication Maneger/CPLD/LCTL_1.2/CPLD_LCTL.vhd" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_latch1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lpm_latch1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_latch1-SYN " "Info: Found design unit 1: lpm_latch1-SYN" {  } { { "lpm_latch1.vhd" "" { Text "E:/Communication Maneger/CPLD/LCTL_1.2/lpm_latch1.vhd" 19 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_latch1 " "Info: Found entity 1: lpm_latch1" {  } { { "lpm_latch1.vhd" "" { Text "E:/Communication Maneger/CPLD/LCTL_1.2/lpm_latch1.vhd" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_latch2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lpm_latch2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_latch2-SYN " "Info: Found design unit 1: lpm_latch2-SYN" {  } { { "lpm_latch2.vhd" "" { Text "E:/Communication Maneger/CPLD/LCTL_1.2/lpm_latch2.vhd" 18 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_latch2 " "Info: Found entity 1: lpm_latch2" {  } { { "lpm_latch2.vhd" "" { Text "E:/Communication Maneger/CPLD/LCTL_1.2/lpm_latch2.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus42/libraries/megafunctions/lpm_latch.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_latch.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_latch " "Info: Found entity 1: lpm_latch" {  } { { "lpm_latch.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_latch.tdf" 40 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "158 " "Info: Implemented 158 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "47 " "Info: Implemented 47 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "20 " "Info: Implemented 20 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "77 " "Info: Implemented 77 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "6 " "Info: Implemented 6 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 14 15:09:32 2007 " "Info: Processing ended: Fri Sep 14 15:09:32 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}