cpld_lctl.map.rpt

CPLD的例子程序1,EPM7128芯片,ISA总线

; lpm_latch:MD1_latch|q[7]~0                              ;    ;
; lpm_latch:MD2_latch|q[7]~0                              ;    ;
; lpm_latch:MD3_latch|q[7]~0                              ;    ;
; lpm_latch:MD4_latch|q[7]~0                              ;    ;
; lpm_latch:MD5_latch|q[7]~0                              ;    ;
; lpm_latch:MD1_latch|q[6]~1                              ;    ;
; lpm_latch:MD2_latch|q[6]~1                              ;    ;
; lpm_latch:MD3_latch|q[6]~1                              ;    ;
; lpm_latch:MD4_latch|q[6]~1                              ;    ;
; lpm_latch:MD5_latch|q[6]~1                              ;    ;
; lpm_latch:MD1_latch|q[5]~2                              ;    ;
; lpm_latch:MD2_latch|q[5]~2                              ;    ;
; lpm_latch:MD3_latch|q[5]~2                              ;    ;
; lpm_latch:MD4_latch|q[5]~2                              ;    ;
; lpm_latch:MD5_latch|q[5]~2                              ;    ;
; lpm_latch:MD1_latch|q[4]~3                              ;    ;
; lpm_latch:MD2_latch|q[4]~3                              ;    ;
; lpm_latch:MD3_latch|q[4]~3                              ;    ;
; lpm_latch:MD4_latch|q[4]~3                              ;    ;
; lpm_latch:MD5_latch|q[4]~3                              ;    ;
; lpm_latch:MD1_latch|q[3]~4                              ;    ;
; lpm_latch:MD2_latch|q[3]~4                              ;    ;
; lpm_latch:MD3_latch|q[3]~4                              ;    ;
; lpm_latch:MD4_latch|q[3]~4                              ;    ;
; lpm_latch:MD5_latch|q[3]~4                              ;    ;
; lpm_latch:MD1_latch|q[2]~5                              ;    ;
; lpm_latch:MD2_latch|q[2]~5                              ;    ;
; lpm_latch:MD3_latch|q[2]~5                              ;    ;
; lpm_latch:MD4_latch|q[2]~5                              ;    ;
; lpm_latch:MD5_latch|q[2]~5                              ;    ;
; lpm_latch:MD1_latch|q[1]~6                              ;    ;
; lpm_latch:MD2_latch|q[1]~6                              ;    ;
; lpm_latch:MD3_latch|q[1]~6                              ;    ;
; lpm_latch:MD4_latch|q[1]~6                              ;    ;
; lpm_latch:MD5_latch|q[1]~6                              ;    ;
; lpm_latch:MD1_latch|q[0]~7                              ;    ;
; lpm_latch:MD2_latch|q[0]~7                              ;    ;
; lpm_latch:MD3_latch|q[0]~7                              ;    ;
; lpm_latch:MD4_latch|q[0]~7                              ;    ;
; lpm_latch:MD5_latch|q[0]~7                              ;    ;
; Number of buffers inserted to break combinational loops ; 48 ;
+---------------------------------------------------------+----+


+---------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                   ;
+------------------------------+------------+------+------------------------------------+
; Compilation Hierarchy Node   ; Macrocells ; Pins ; Full Hierarchy Name                ;
+------------------------------+------------+------+------------------------------------+
; |CPLD_LCTL                   ; 77         ; 75   ; |CPLD_LCTL                         ;
;    |lpm_latch:MD1_latch|     ; 8          ; 0    ; |CPLD_LCTL|lpm_latch:MD1_latch     ;
;    |lpm_latch:MD2_latch|     ; 8          ; 0    ; |CPLD_LCTL|lpm_latch:MD2_latch     ;
;    |lpm_latch:MD3_latch|     ; 8          ; 0    ; |CPLD_LCTL|lpm_latch:MD3_latch     ;
;    |lpm_latch:MD4_latch|     ; 8          ; 0    ; |CPLD_LCTL|lpm_latch:MD4_latch     ;
;    |lpm_latch:MD5_latch|     ; 8          ; 0    ; |CPLD_LCTL|lpm_latch:MD5_latch     ;
;    |lpm_latch:lpm_latch_DKO| ; 8          ; 0    ; |CPLD_LCTL|lpm_latch:lpm_latch_DKO ;
+------------------------------+------------+------+------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Communication Maneger/CPLD/LCTL_1.2/CPLD_LCTL.map.eqn.


+-------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                            ;
+----------------------------------+-----------------+--------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                 ;
+----------------------------------+-----------------+--------------------------------------------------------------+
; CPLD_LCTL.vhd                    ; yes             ; E:/Communication Maneger/CPLD/LCTL_1.2/CPLD_LCTL.vhd         ;
; lpm_latch.tdf                    ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_latch.tdf    ;
; lpm_constant.inc                 ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_constant.inc ;
+----------------------------------+-----------------+--------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 77                   ;
; Total registers      ; 0                    ;
; I/O pins             ; 75                   ;
; Shareable expanders  ; 6                    ;
; Parallel expanders   ; 8                    ;
; Maximum fan-out node ; RST                  ;
; Maximum fan-out      ; 48                   ;
; Total fan-out        ; 1086                 ;
; Average fan-out      ; 6.87                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Fri Sep 14 15:09:28 2007
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off CPLD_LCTL -c CPLD_LCTL
Info: Found 2 design units, including 1 entities, in source file CPLD_LCTL.vhd
    Info: Found design unit 1: CPLD_LCTL-BEHAVE
    Info: Found entity 1: CPLD_LCTL
Info: Found 2 design units, including 1 entities, in source file lpm_latch1.vhd
    Info: Found design unit 1: lpm_latch1-SYN
    Info: Found entity 1: lpm_latch1
Info: Found 2 design units, including 1 entities, in source file lpm_latch2.vhd
    Info: Found design unit 1: lpm_latch2-SYN
    Info: Found entity 1: lpm_latch2
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_latch.tdf
    Info: Found entity 1: lpm_latch
Info: Implemented 158 device resources after synthesis - the final resource count might be different
    Info: Implemented 47 input pins
    Info: Implemented 20 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 77 macrocells
    Info: Implemented 6 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Sep 14 15:09:32 2007
    Info: Elapsed time: 00:00:05