cpld_lctl.qsf

CPLD的例子程序1,EPM7128芯片,ISA总线

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		CPLD_LCTL_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:47:56  OCTOBER 04, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 4.2
set_global_assignment -name VHDL_FILE CPLD_LCTL.vhd
set_global_assignment -name VHDL_FILE lpm_latch1.vhd
set_global_assignment -name VHDL_FILE lpm_latch2.vhd

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY MAX3000A
set_global_assignment -name TOP_LEVEL_ENTITY CPLD_LCTL
set_global_assignment -name USER_LIBRARIES "E:\\Sean\\My Designs\\design_test\\429/"

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPM3128ATC144-10"

# Simulator Assignments
# =====================
set_global_assignment -name GLITCH_INTERVAL "1 "

# ----------------
# start CLOCK(IOW)

	# Timing Assignments
	# ==================
	set_global_assignment -name FMAX_REQUIREMENT "1.5 MHz" -section_id IOW
	set_global_assignment -name DUTY_CYCLE 50 -section_id IOW
	set_global_assignment -name INVERT_BASE_CLOCK OFF -section_id IOW
	set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id IOW
	set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id IOW

# end CLOCK(IOW)
# --------------

# -----------------------
# start ENTITY(CPLD_LCTL)

	# Timing Assignments
	# ==================
	set_instance_assignment -name CLOCK_SETTINGS IOW -to IOW

# end ENTITY(CPLD_LCTL)
# ---------------------