📄 cpld_lctl.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY CPLD_LCTL IS
PORT (
--============== PC104 SINGALS ===================
RST : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
D : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
AEN : IN STD_LOGIC;
IOW : IN STD_LOGIC;
IOR : IN STD_LOGIC;
-- IOCS16 : OUT STD_LOGIC;
IRQ1 : OUT STD_LOGIC;
IRQ2 : OUT STD_LOGIC;
IRQ3 : OUT STD_LOGIC;
IRQ4 : OUT STD_LOGIC;
-- CLK_IN : IN STD_LOGIC;
-- K : IN STD_LOGIC_VECTOR(9 DOWNTO 5);
--============== MCU SIGNSLS =====================
MCS : IN STD_LOGIC;
MWR : IN STD_LOGIC;
MD : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
MA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
PPS : IN STD_LOGIC;
--============== DIO SIGNSLS =====================
DK_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DK_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--============== 16C554 SIGNSLS =====================
INT_COM : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CS_COM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE BEHAVE OF CPLD_LCTL IS
--SIGNAL CS : STD_LOGIC;
SIGNAL IMREG_SEL : STD_LOGIC;
--SIGNAL ISSEL : STD_LOGIC;
SIGNAL IMREG : STD_LOGIC;
SIGNAL RD_ISREG,RD_IMREG,WR_IMREG : STD_LOGIC;
SIGNAL WR_MD1 : STD_LOGIC;
SIGNAL WR_MD2 : STD_LOGIC;
SIGNAL WR_MD3 : STD_LOGIC;
SIGNAL WR_MD4 : STD_LOGIC;
SIGNAL WR_MD5 : STD_LOGIC;
SIGNAL REG_DATA1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL REG_DATA2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL REG_DATA3 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL REG_DATA4 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL REG_DATA5 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CS_GPS : STD_LOGIC;
SIGNAL DKCS,DKWR,DKRD : STD_LOGIC;
SIGNAL SEND_DATA1 : STD_LOGIC;
--SIGNAL CLEAR_IRQ : STD_LOGIC;
SIGNAL IRQ_SEL : STD_LOGIC;
SIGNAL IRQ_TEMP : STD_LOGIC;
SIGNAL CS_PH, CS_PG, CS_PF, CS_PE, CS_PD, CS_PC, CS_PB, CS_PA, CS_PI : STD_LOGIC;
COMPONENT lpm_latch
GENERIC (
lpm_width : NATURAL;
lpm_type : STRING
);
PORT (
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
gate : IN STD_LOGIC ;
aset : IN STD_LOGIC
);
END COMPONENT;
COMPONENT lpm_latch1
PORT (
q : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
gate : IN STD_LOGIC ;
aset : IN STD_LOGIC
);
END COMPONENT;
BEGIN
--=============================== REG ====================================
CS_GPS <= '0' WHEN A(11 DOWNTO 4) = X"38" AND AEN = '0' ELSE '1'; --380
--IOCS16 <= 'Z';
--=========================== READ DATA ===============================
WR_MD1 <= '1' WHEN MCS = '0' AND MWR='0' AND MA = "0000" ELSE '0';
WR_MD2 <= '1' WHEN MCS = '0' AND MWR='0' AND MA = "0001" ELSE '0';
WR_MD3 <= '1' WHEN MCS = '0' AND MWR='0' AND MA = "0010" ELSE '0';
WR_MD4 <= '1' WHEN MCS = '0' AND MWR='0' AND MA = "0011" ELSE '0';
WR_MD5 <= '1' WHEN MCS = '0' AND MWR='0' AND MA = "0100" ELSE '0';
MD1_latch : lpm_latch
GENERIC MAP (
lpm_width => 8,
lpm_type => "LPM_LATCH"
)
PORT MAP (
data => MD,
gate => WR_MD1,
aset => RST,
q => REG_DATA1
);
MD2_latch : lpm_latch
GENERIC MAP (
lpm_width => 8,
lpm_type => "LPM_LATCH"
)
PORT MAP (
data => MD,
gate => WR_MD2,
aset => RST,
q => REG_DATA2
);
MD3_latch : lpm_latch
GENERIC MAP (
lpm_width => 8,
lpm_type => "LPM_LATCH"
)
PORT MAP (
data => MD,
gate => WR_MD3,
aset => RST,
q => REG_DATA3
);
MD4_latch : lpm_latch
GENERIC MAP (
lpm_width => 8,
lpm_type => "LPM_LATCH"
)
PORT MAP (
data => MD,
gate => WR_MD4,
aset => RST,
q => REG_DATA4
);
MD5_latch : lpm_latch
GENERIC MAP (
lpm_width => 8,
lpm_type => "LPM_LATCH"
)
PORT MAP (
data => MD,
gate => WR_MD5,
aset => RST,
q => REG_DATA5
);
D <= INT_COM WHEN RD_ISREG = '1' ELSE
REG_DATA1 WHEN CS_GPS = '0' AND IOR = '0' AND A(2 downto 0) = "000" ELSE
REG_DATA2 WHEN CS_GPS = '0' AND IOR = '0' AND A(2 downto 0) = "001" ELSE
REG_DATA3 WHEN CS_GPS = '0' AND IOR = '0' AND A(2 downto 0) = "010" ELSE
REG_DATA4 WHEN CS_GPS = '0' AND IOR = '0' AND A(2 downto 0) = "011" ELSE
REG_DATA5 WHEN CS_GPS = '0' AND IOR = '0' AND A(2 downto 0) = "100" ELSE
DK_IN WHEN DKRD = '1' ELSE
"ZZZZZZZZ";
--================================ SEND DK DATA ==============================
DKCS <= '0' WHEN A(11 DOWNTO 3) = "001101110" AND AEN = '0' ELSE '1'; --370
DKWR <= '1' WHEN DKCS = '0' AND IOW ='0' AND A(2 downto 0) = "000" ELSE '0';
DKRD <= '1' WHEN DKCS = '0' AND IOR ='0' AND A(2 downto 0) = "000" ELSE '0';
lpm_latch_DKO : lpm_latch
GENERIC MAP (
lpm_width => 8,
lpm_type => "LPM_LATCH"
)
PORT MAP (
data => D(7 DOWNTO 0),
gate => DKWR,
aset => RST,
q => DK_OUT
);
--============================== COM ========================================
CS_COM(7 DOWNTO 0) <= CS_PH & CS_PG &CS_PF &CS_PE & CS_PD & CS_PC & CS_PB & CS_PA;
CS_PA <= '0' WHEN AEN = '0' AND A(11 DOWNTO 3) = "001111111" ELSE '1';--3F8
CS_PB <= '0' WHEN AEN = '0' AND A(11 DOWNTO 3) = "001011111" ELSE '1';--2F8
CS_PC <= '0' WHEN AEN = '0' AND A(11 DOWNTO 3) = "001111101" ELSE '1';--3E8
CS_PD <= '0' WHEN AEN = '0' AND A(11 DOWNTO 3) = "001011101" ELSE '1';--2E8
CS_PE <= '0' WHEN AEN = '0' AND A(11 DOWNTO 3) = "001110101" ELSE '1';--3A8
CS_PF <= '0' WHEN AEN = '0' AND A(11 DOWNTO 3) = "001010101" ELSE '1';--2A8
CS_PG <= '0' WHEN AEN = '0' AND A(11 DOWNTO 3) = "001110001" ELSE '1';--388
CS_PH <= '0' WHEN AEN = '0' AND A(11 DOWNTO 3) = "001010001" ELSE '1';--288
CS_PI <= '0' WHEN AEN = '0' AND A(11 DOWNTO 2) = "0010001000" ELSE '1';--220
--============================== INT =========================================
RD_ISREG <= '1' WHEN CS_PI = '0' AND IOR = '0' AND A(1 DOWNTO 0) = "00" ELSE '0';
RD_IMREG <= '1' WHEN CS_PI = '0' AND IOR = '0' AND A(1 DOWNTO 0) = "01" ELSE '0';
WR_IMREG <= '1' WHEN CS_PI = '0' AND IOW = '0' AND A(1 DOWNTO 0) = "01" ELSE '0';
IRQ1 <= INT_COM(3) AND INT_COM(2) AND INT_COM(1) AND INT_COM(0);
IRQ2 <= INT_COM(7) AND INT_COM(6) AND INT_COM(5) AND INT_COM(4);
IRQ3 <= PPS;
IRQ4 <= DK_IN(3) AND DK_IN(2) AND DK_IN(1) AND DK_IN(0) ;
END BEHAVE;
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