📄 cpld_lctl.fit.rpt
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+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 32.00) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 0 ;
; 3 - 5 ; 0 ;
; 6 - 8 ; 0 ;
; 9 - 11 ; 0 ;
; 12 - 14 ; 0 ;
; 15 - 17 ; 0 ;
; 18 - 20 ; 0 ;
; 21 - 23 ; 0 ;
; 24 - 26 ; 0 ;
; 27 - 29 ; 0 ;
; 30 - 32 ; 6 ;
; 33 - 35 ; 2 ;
+-----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 9.63) ; Number of LABs (Total = 8) ;
+----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 2 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 0 ;
; 10 ; 1 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
; 16 ; 1 ;
+----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 8 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 4.50) ; Number of LABs (Total = 6) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 2 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 6 ;
+-------------------------------------------------+-----------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------+
; A ; LC9 ; A[4], A[8], A[5], A[7], A[3], AEN, A[11], A[10], A[9], A[6] ; CS_COM[3] ;
; A ; LC11 ; A[4], A[8], A[5], A[7], A[3], AEN, A[11], A[10], A[9], A[6] ; CS_COM[1] ;
; A ; LC12 ; A[5], A[8], A[7], A[3], AEN, A[11], A[10], A[9], A[6], A[4] ; CS_COM[7] ;
; A ; LC13 ; A[7], A[3], AEN, A[11], A[10], A[9], A[6], A[4], A[5], A[8] ; CS_COM[6] ;
; A ; LC14 ; A[8], A[4], A[5], A[7], A[3], AEN, A[11], A[10], A[9], A[6] ; CS_COM[2] ;
; A ; LC4 ; A[5], A[7], A[3], AEN, A[11], A[10], A[9], A[6], A[8], A[4] ; CS_COM[0] ;
; A ; LC7 ; MD[7], MA[1], MA[2], MA[3], MCS, MWR, MA[0], lpm_latch:MD2_latch|q[7]~704, RST ; D~11274, lpm_latch:MD2_latch|q[7]~704 ;
; A ; LC8 ; A[8], A[5], A[7], A[3], AEN, A[11], A[10], A[9], A[6], A[4] ; CS_COM[4] ;
; A ; LC6 ; A[8], A[5], A[7], A[3], AEN, A[11], A[10], A[9], A[6], A[4] ; CS_COM[5] ;
; A ; LC15 ; MD[7], MA[1], MA[2], MA[3], MCS, MWR, MA[0], lpm_latch:MD4_latch|q[7]~704, RST ; D~11274, lpm_latch:MD4_latch|q[7]~704 ;
; A ; LC5 ; D[7], IOW, AEN, A[11], A[10], A[9], A[6], A[8], A[4], A[5], A[7], A[3], A[2], A[1], A[0], lpm_latch:lpm_latch_DKO|q[7]~906, RST ; lpm_latch:lpm_latch_DKO|q[7]~906, DK_OUT[7] ;
; A ; LC16 ; D[6], IOW, AEN, A[11], A[10], A[9], A[6], A[8], A[4], A[5], A[7], A[3], A[2], A[1], A[0], lpm_latch:lpm_latch_DKO|q[6]~912, RST ; lpm_latch:lpm_latch_DKO|q[6]~912, DK_OUT[6] ;
; A ; LC3 ; D[5], IOW, AEN, A[11], A[10], A[9], A[6], A[8], A[4], A[5], A[7], A[3], A[2], A[1], A[0], lpm_latch:lpm_latch_DKO|q[5]~918, RST ; lpm_latch:lpm_latch_DKO|q[5]~918, DK_OUT[5] ;
; A ; LC10 ; MD[7], MA[2], MA[3], MCS, MWR, MA[1], MA[0], lpm_latch:MD1_latch|q[7]~704, RST ; lpm_latch:MD1_latch|q[7]~704, D~11274 ;
; A ; LC1 ; D[4], IOW, AEN, A[11], A[10], A[9], A[6], A[8], A[4], A[5], A[7], A[3], A[2], A[1], A[0], lpm_latch:lpm_latch_DKO|q[4]~924, RST ; lpm_latch:lpm_latch_DKO|q[4]~924, DK_OUT[4] ;
; B ; LC30 ; RST, lpm_latch:MD5_latch|q[6]~710, MA[2], MA[3], MCS, MWR, MA[1], MA[0], MD[6] ; D~11285, lpm_latch:MD5_latch|q[6]~710 ;
; B ; LC22 ; RST, lpm_latch:MD1_latch|q[6]~710, MA[2], MA[3], MCS, MWR, MA[1], MA[0], MD[6] ; lpm_latch:MD1_latch|q[6]~710, D~11285 ;
; B ; LC17 ; D[2], IOW, AEN, A[11], A[10], A[9], A[6], A[8], A[4], A[5], A[7], A[3], A[2], A[1], A[0], lpm_latch:lpm_latch_DKO|q[2]~936, RST ; lpm_latch:lpm_latch_DKO|q[2]~936, DK_OUT[2] ;
; B ; LC32 ; RST, lpm_latch:MD3_latch|q[6]~710, MA[2], MA[3], MCS, MWR, MA[1], MA[0], MD[6] ; D~11285, lpm_latch:MD3_latch|q[6]~710 ;
; B ; LC20 ; RST, lpm_latch:MD4_latch|q[6]~710, MA[1], MA[2], MA[3], MCS, MWR, MA[0], MD[6] ; D~11285, lpm_latch:MD4_latch|q[6]~710 ;
; B ; LC26 ; RST, lpm_latch:MD2_latch|q[6]~710, MA[1], MA[2], MA[3], MCS, MWR, MA[0], MD[6] ; D~11285, lpm_latch:MD2_latch|q[6]~710 ;
; B ; LC18 ; INT_COM[6], A[8], A[5], A[7], A[3], A[2], A[1], A[0], AEN, A[11], A[10], A[9], A[6], A[4], IOR, RD_ISREG~26, DK_IN[6], D~11346, D~11347, D~11348, D~11349, D~11366 ; D~11285 ;
; B ; LC19 ; D~11325, lpm_latch:MD2_latch|q[6]~710, lpm_latch:MD3_latch|q[6]~710, lpm_latch:MD4_latch|q[6]~710, lpm_latch:MD5_latch|q[6]~710, RD_ISREG~26, D~11346, A[1], A[0], A[2], A[7], A[5], A[8], AEN, A[11], A[10], A[9], A[6], A[4], IOR, D~11347, D~11348, D~11349, lpm_latch:MD1_latch|q[6]~710 ; D[6] ;
; C ; LC42 ; RST, lpm_latch:MD4_latch|q[5]~716, MA[1], MA[2], MA[3], MCS, MWR, MA[0], MD[5] ; D~11291, lpm_latch:MD4_latch|q[5]~716 ;
; C ; LC40 ; RST, lpm_latch:MD5_latch|q[5]~716, MA[2], MA[3], MCS, MWR, MA[1], MA[0], MD[5] ; D~11291, lpm_latch:MD5_latch|q[5]~716 ;
; C ; LC41 ; RST, lpm_latch:MD2_latch|q[5]~716, MA[1], MA[2], MA[3], MCS, MWR, MA[0], MD[5] ; D~11291, lpm_latch:MD2_latch|q[5]~716 ;
; C ; LC34 ; INT_COM[5], A[8], A[5], A[7], A[3], A[2], A[1], A[0], AEN, A[11], A[10], A[9], A[6], A[4], IOR, RD_ISREG~27, DK_IN[5], D~11350, D~11351, D~11352, D~11353, D~11367 ; D~11291 ;
; C ; LC33 ; D[0], IOW, AEN, A[11], A[10], A[9], A[6], A[8], A[4], A[5], A[7], A[3], A[2], A[1], A[0], lpm_latch:lpm_latch_DKO|q[0]~948, RST ; lpm_latch:lpm_latch_DKO|q[0]~948, DK_OUT[0] ;
; C ; LC38 ; RST, lpm_latch:MD3_latch|q[5]~716, MA[2], MA[3], MCS, MWR, MA[1], MA[0], MD[5] ; D~11291, lpm_latch:MD3_latch|q[5]~716 ;
; C ; LC45 ; RST, lpm_latch:MD1_latch|q[5]~716, MA[2], MA[3], MCS, MWR, MA[1], MA[0], MD[5] ; lpm_latch:MD1_latch|q[5]~716, D~11291 ;
; C ; LC35 ; D~11328, lpm_latch:MD2_latch|q[5]~716, lpm_latch:MD3_latch|q[5]~716, lpm_latch:MD4_latch|q[5]~716, lpm_latch:MD5_latch|q[5]~716, RD_ISREG~27, D~11350, A[1], A[0], A[2], A[7], A[5], A[8], AEN, A[11], A[10], A[9], A[6], A[4], IOR, D~11351, D~11352, D~11353, lpm_latch:MD1_latch|q[5]~716 ; D[5] ;
; D ; LC52 ; RST, lpm_latch:MD1_latch|q[3]~728, MA[2], MA[3], MCS, MWR, MA[1], MA[0], MD[3] ; lpm_latch:MD1_latch|q[3]~728, D~11303 ;
; D ; LC56 ; RST, lpm_latch:MD3_latch|q[1]~740, MA[2], MA[3], MCS, MWR, MA[1], MA[0], MD[1] ; D~11315, lpm_latch:MD3_latch|q[1]~740 ;
; D ; LC62 ; RST, lpm_latch:MD4_latch|q[4]~722, MA[1], MA[2], MA[3], MCS, MWR, MA[0], MD[4] ; D~11297, lpm_latch:MD4_latch|q[4]~722 ;
; D ; LC54 ; RST, lpm_latch:MD2_latch|q[4]~722, MA[1], MA[2], MA[3], MCS, MWR, MA[0], MD[4] ; D~11297, lpm_latch:MD2_latch|q[4]~722 ;
; D ; LC57 ; RST, lpm_latch:MD4_latch|q[3]~728, MA[1], MA[2], MA[3], MCS, MWR, MA[0], MD[3] ; D~11303, lpm_latch:MD4_latch|q[3]~728 ;
; D ; LC58 ; RST, lpm_latch:MD2_latch|q[3]~728, MA[1], MA[2], MA[3], MCS, MWR, MA[0], MD[3] ; D~11303, lpm_latch:MD2_latch|q[3]~728 ;
; D ; LC49 ; INT_COM[7], INT_COM[6], INT_COM[5], INT_COM[4] ; IRQ2 ;
; D ; LC51 ; PPS ; IRQ3 ;
; D ; LC53 ; MD[7], MA[2], MA[3], MCS, MWR, MA[1], MA[0], lpm_latch:MD5_latch|q[7]~704, RST ; D~11274, lpm_latch:MD5_latch|q[7]~704 ;
; D ; LC59 ; RST, lpm_latch:MD5_latch|q[4]~722, MA[2], MA[3], MCS, MWR, MA[1], MA[0], MD[4] ; D~11297, lpm_latch:MD5_latch|q[4]~722 ;
; D ; LC64 ; RST, lpm_latch:MD5_latch|q[3]~728, MA[2], MA[3], MCS, MWR, MA[1], MA[0], MD[3] ; D~11303, lpm_latch:MD5_latch|q[3]~728 ;
; D ; LC60 ; RST, lpm_latch:MD5_latch|q[1]~740, MA[2], MA[3], MCS, MWR, MA[1], MA[0], MD[1] ; D~11315, lpm_latch:MD5_latch|q[1]~740 ;
; D ; LC61 ; MD[7], MA[2], MA[3], MCS, MWR, MA[1], MA[0], lpm_latch:MD3_latch|q[7]~704, RST ; D~11274, lpm_latch:MD3_latch|q[7]~704 ;
; D ; LC55 ; RST, lpm_latch:MD3_latch|q[4]~722, MA[2], MA[3], MCS, MWR, MA[1], MA[0], MD[4] ; D~11297, lpm_latch:MD3_latch|q[4]~722 ;
; D ; LC63 ; RST, lpm_latch:MD1_latch|q[4]~722, MA[2], MA[3], MCS, MWR, MA[1], MA[0], MD[4] ; lpm_latch:MD1_latch|q[4]~722, D~11297 ;
; D ; LC50 ; RST, lpm_latch:MD3_latch|q[3]~728, MA[2], MA[3], MCS, MWR, MA[1], MA[0], MD[3] ; D~11303, lpm_latch:MD3_latch|q[3]~728 ;
; E ; LC70 ; DK_IN[3], DK_IN[2], DK_IN[1], DK_IN[0] ; IRQ4 ;
; E ; LC65 ; INT_COM[3], INT_COM[2], INT_COM[1], INT_COM[0] ⌨️ 快捷键说明
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