protect.vht

来自「这是一个开发gal16v8器件的详细源代码」· VHT 代码 · 共 56 行

-- VHDL test bench created from symbol protect.sym -- Aug 16 14:36:40 2006

LIBRARY vanmacro;
USE vanmacro.components.ALL;
LIBRARY ieee;
LIBRARY generics;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE generics.components.ALL;

entity testbench is
end testbench;

Architecture behavior of testbench is

   signal        P : std_logic;
   signal      R1A : std_logic;
   signal      R1B : std_logic;
   signal       R2 : std_logic;
   signal       R3 : std_logic;
   signal        S : std_logic;
   signal      PSO : std_logic;
   signal       Q1 : std_logic;
   signal       Q2 : std_logic;
   signal       Q3 : std_logic;
   signal    RESET : std_logic;

   component PROTECT
      Port (       P : In    std_logic;
                 R1A : In    std_logic;
                 R1B : In    std_logic;
                  R2 : In    std_logic;
                  R3 : In    std_logic;
                   S : In    std_logic;
                 PSO : Out   std_logic;
                  Q1 : Out   std_logic;
                  Q2 : Out   std_logic;
                  Q3 : Out   std_logic;
               RESET : Out   std_logic );
   end component;

begin
   UUT : PROTECT
      Port Map ( P=>P, PSO=>PSO, Q1=>Q1, Q2=>Q2, Q3=>Q3, R1A=>R1A,
                 R1B=>R1B, R2=>R2, R3=>R3, RESET=>RESET, S=>S );

-- *** Test Bench - User Defined Section ***
   TB : process
   begin
      wait; -- will wait forever
   end process;
-- *** End Test Bench - User Defined Section ***

end behavior;