📄 hex2led_common_cathode.v
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////////////////////////////////////////////////////////////////////////////////// *****************************************************************************// * RICHIC CONFIDENTIAL PROPRIETARY NOTE *// * *// * This software contains information confidential and proprietary to *// * RicHic Inc.It shall not be reproduced in whole or in part or transferred *// * to other documents, or disclosed to third parties, or used for any *// * purpose other than that for which it was obtained, without the prior *// * written consent of RicHic Inc. *// * (c) 2003, 2004, 2005 RicHic Inc. *// * All rights reserved * /* ****************************************************************************** * * 更多精彩内容:http://www.richic.com ** ** 1、本程序由瑞芯科技 逻辑设计部提供 ** 2、本程序在瑞芯科技 FPGA开发系统中验证通过 ** 3、瑞芯科技网站提供更多参考设计,以提高朋友们的设计水平,请访问我们的网站 ** 4、瑞芯科技欢迎朋友们提供精彩设计 ** ** (C) 2004 fpga_ic@richic.com; ** http://www.richic.com ** ********************************************************************************/module hex2led_common_cathode (hex, led) ;input [3:0] hex;output [6:0] led;reg [6:0] led;//hex-to-seven-segment decoder//// segment encoding// 0// --- // 5 | | 1// --- <- 6// 4 | | 2// ---// 3always @(hex)begin case (hex) //数值 共阴极段码 4'b0001 : led = 7'b0000110; //1 06 4'b0010 : led = 7'b1011011; //2 5B 4'b0011 : led = 7'b1001111; //3 4F 4'b0100 : led = 7'b1100110; //4 66 4'b0101 : led = 7'b1101101; //5 6D 4'b0110 : led = 7'b1111101; //6 7D 4'b0111 : led = 7'b0000111; //7 07 4'b1000 : led = 7'b1111111; //8 7F 4'b1001 : led = 7'b1101111; //9 6F 4'b1010 : led = 7'b1110111; //A 77 4'b1011 : led = 7'b1111100; //b 7C 4'b1100 : led = 7'b0111001; //C 39 4'b1101 : led = 7'b1011110; //d 5E 4'b1110 : led = 7'b1111001; //E 79 4'b1111 : led = 7'b1110001; //F 71 default : led = 7'b0111111; //0 3F endcaseendendmodule
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