keyboard_test1_top.v

ps2_键盘控制器源码verilog源码

module  keyboard_test1_top (
    ps2k_clk,
    ps2k_data,
    ps2m_clk,
    ps2m_data,
    seg,    
    clk,
    rst_n // synthesis attribute clock_buffer of rst_n is ibufg;    
    );

inout               ps2k_clk;
inout               ps2k_data;
inout               ps2m_clk;
inout               ps2m_data;
output  [11:0]      seg ;
input               clk;
input               rst_n; 


wire    [7 :0]      r_data1;
wire    [7 :0]      w_data1;
wire                busy1;
wire                complete1;
wire    [1 :0]      error1;

wire    [7 :0]      r_data2;
wire    [7 :0]      w_data2;
wire                busy2;
wire                complete2;
wire    [1 :0]      error2;


led_top led_top_inst(
    .seg    ( seg   ),    
    .clk    ( clk   ),
    .rst_n  ( rst_n ), 
    .data   ( {r_data1,r_data2} ),
    .dot    ( 4'b0000)
    );

keyboard_test1 keyboard_test1_inst1(
    .PS2K_DATA  (ps2k_data),
    .PS2K_CLK   (ps2k_clk),
    .R_DATA     (r_data1),
    .W_DATA     (w_data1),
    .BUSY       (busy1),
    .Complete   (complete1),
    .Error      (error1),
    .RW         (1'b1),
    .ENA        (1'b1),
    .CLK        (clk),
    .CLR        (rst_n)
    );


keyboard_test1 keyboard_test1_inst2(
    .PS2K_DATA  (ps2m_data),
    .PS2K_CLK   (ps2m_clk),
    .R_DATA     (r_data2),
    .W_DATA     (w_data2),
    .BUSY       (busy2),
    .Complete   (complete2),
    .Error      (error2),
    .RW         (1'b1),
    .ENA        (1'b1),
    .CLK        (clk),
    .CLR        (rst_n)
    );

endmodule