keyboard.map.qmsg

keyboard 的verilog 代码 代码绝对经典

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 27 01:04:23 2007 " "Info: Processing started: Sat Oct 27 01:04:23 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off keyboard -c keyboard " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off keyboard -c keyboard" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Critical Warning" "WVRFX_VERI_PORT_DECL_WITH_DIMS" "col packed keyboard.v(3) " "Critical Warning (10226): Verilog HDL Port Declaration warning at keyboard.v(3): port declaration for \"col\" declares packed dimensions but the data type declaration does not" {  } { { "keyboard.v" "" { Text "D:/keyboard/keyboard.v" 3 0 0 } }  } 1 10226 "Verilog HDL Port Declaration warning at %3!s!: port declaration for \"%1!s!\" declares %2!s! dimensions but the data type declaration does not" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "col keyboard.v(7) " "Info (10151): Verilog HDL Declaration information at keyboard.v(7): \"col\" is declared here" {  } { { "keyboard.v" "" { Text "D:/keyboard/keyboard.v" 7 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0}
{ "Critical Warning" "WVRFX_VERI_PORT_DECL_WITH_DIMS" "code packed keyboard.v(5) " "Critical Warning (10226): Verilog HDL Port Declaration warning at keyboard.v(5): port declaration for \"code\" declares packed dimensions but the data type declaration does not" {  } { { "keyboard.v" "" { Text "D:/keyboard/keyboard.v" 5 0 0 } }  } 1 10226 "Verilog HDL Port Declaration warning at %3!s!: port declaration for \"%1!s!\" declares %2!s! dimensions but the data type declaration does not" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "code keyboard.v(7) " "Info (10151): Verilog HDL Declaration information at keyboard.v(7): \"code\" is declared here" {  } { { "keyboard.v" "" { Text "D:/keyboard/keyboard.v" 7 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0}
{ "Critical Warning" "WVRFX_VERI_PORT_DECL_WITH_DIMS" "row packed keyboard.v(72) " "Critical Warning (10226): Verilog HDL Port Declaration warning at keyboard.v(72): port declaration for \"row\" declares packed dimensions but the data type declaration does not" {  } { { "keyboard.v" "" { Text "D:/keyboard/keyboard.v" 72 0 0 } }  } 1 10226 "Verilog HDL Port Declaration warning at %3!s!: port declaration for \"%1!s!\" declares %2!s! dimensions but the data type declaration does not" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "row keyboard.v(75) " "Info (10151): Verilog HDL Declaration information at keyboard.v(75): \"row\" is declared here" {  } { { "keyboard.v" "" { Text "D:/keyboard/keyboard.v" 75 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "keyboard.v 3 3 " "Info: Found 3 design units, including 3 entities, in source file keyboard.v" { { "Info" "ISGN_ENTITY_NAME" "1 keyboard " "Info: Found entity 1: keyboard" {  } { { "keyboard.v" "" { Text "D:/keyboard/keyboard.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 synch " "Info: Found entity 2: synch" {  } { { "keyboard.v" "" { Text "D:/keyboard/keyboard.v" 53 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 row_signal " "Info: Found entity 3: row_signal" {  } { { "keyboard.v" "" { Text "D:/keyboard/keyboard.v" 71 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EVRFX_VERI_INDEX_NON_ARRAY" "row keyboard.v(78) " "Error (10053): Verilog HDL error at keyboard.v(78): variable \"row\" cannot be indexed because it is not declared as an array" {  } { { "keyboard.v" "" { Text "D:/keyboard/keyboard.v" 78 0 0 } }  } 0 10053 "Verilog HDL error at %2!s!: variable \"%1!s!\" cannot be indexed because it is not declared as an array" 0 0}
{ "Error" "EVRFX_VERI_INDEX_NON_ARRAY" "row keyboard.v(79) " "Error (10053): Verilog HDL error at keyboard.v(79): variable \"row\" cannot be indexed because it is not declared as an array" {  } { { "keyboard.v" "" { Text "D:/keyboard/keyboard.v" 79 0 0 } }  } 0 10053 "Verilog HDL error at %2!s!: variable \"%1!s!\" cannot be indexed because it is not declared as an array" 0 0}
{ "Error" "EVRFX_VERI_INDEX_NON_ARRAY" "row keyboard.v(80) " "Error (10053): Verilog HDL error at keyboard.v(80): variable \"row\" cannot be indexed because it is not declared as an array" {  } { { "keyboard.v" "" { Text "D:/keyboard/keyboard.v" 80 0 0 } }  } 0 10053 "Verilog HDL error at %2!s!: variable \"%1!s!\" cannot be indexed because it is not declared as an array" 0 0}
{ "Error" "EVRFX_VERI_INDEX_NON_ARRAY" "row keyboard.v(81) " "Error (10053): Verilog HDL error at keyboard.v(81): variable \"row\" cannot be indexed because it is not declared as an array" {  } { { "keyboard.v" "" { Text "D:/keyboard/keyboard.v" 81 0 0 } }  } 0 10053 "Verilog HDL error at %2!s!: variable \"%1!s!\" cannot be indexed because it is not declared as an array" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 4 s 3 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "120 " "Info: Allocated 120 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Sat Oct 27 01:04:25 2007 " "Error: Processing ended: Sat Oct 27 01:04:25 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}