keyboard.v

keyboard 的verilog 代码 代码绝对经典

module keyboard(code,col,valid,row,s_row,clk,reset);
input [3:0] row;
output [3:0] col;
input clk,reset,s_row;
output [3:0] code;
output valid;
reg col,code;
reg [5:0] state,next_state;
parameter s_0=6'b000001,s_1=6'b000010,s_2=6'b000100;
parameter s_3=6'b001000,s_4=6'b010000,s_5=6'b100000;
assign valid=((state==s_1)||(state==s_2)||(state==s_3)||(state==s_4))&&row;
always @(row or col)
case({row,col})
8'b0001_0001:code=0;
8'b0001_0010:code=1;
8'b0001_0100:code=2;
8'b0001_1000:code=3;

8'b0010_0001:code=4;
8'b0010_0010:code=5;
8'b0010_0100:code=6;
8'b0010_1000:code=7;

8'b0100_0001:code=8;
8'b0100_0010:code=9;
8'b0100_0100:code=10;
8'b0100_1000:code=11;

8'b1000_0001:code=12;
8'b1000_0010:code=13;
8'b1000_0100:code=14;
8'b1000_1000:code=15;
default: code=0;
endcase

always@(posedge clk or posedge reset)
if(reset) state<=s_0;
else state<=next_state;

always @(state or s_row or row)
begin next_state=state;col=0;
case(state)
s_0: begin col=15; if(s_row) next_state=s_1;end
s_1: begin col=1; if(row) next_state=s_5; else next_state=s_2;end
s_2: begin col=2; if(row) next_state=s_5;else next_state=s_3;end
s_3: begin col=4; if(row) next_state=s_5;else next_state=s_4;end
s_4: begin col=8; if(row) next_state=s_5;else next_state=s_0;end
s_5: begin col=15; if(row==0) next_state=s_0;end
 endcase
end
endmodule

module synch(s_row,row,clk,reset);
output s_row;
input [3:0] row;
input clk,reset;
reg a_row,s_row;
always@(negedge clk or posedge reset )
begin
if(reset) begin
a_row<=0;
s_row<=0; 
end
else begin
a_row<=(row[0]||row[1]||row[2]||row[3]);
s_row<=a_row;
end
end
endmodule

module row_signal(row,key,col);
output [3:0] row;
input[15:0] key;
input[3:0] col;
reg row;
always @(key or col) 
begin
row[0]=key[0]&&col[0]||key[1]&&col[1]||key[2]&&col[2]||key[3]&&col[3];
row[1]=key[4]&&col[0]||key[5]&&col[1]||key[6]&&col[2]||key[7]&&col[3];
row[2]=key[8]&&col[0]||key[9]&&col[1]||key[10]&&col[2]||key[11]&&col[3];
row[3]=key[12]&&col[0]||key[13]&&col[1]||key[14]&&col[2]||key[15]&&col[3];
end
endmodule

module test_keyboard;
wire [3:0] code;
wire valid;
wire[3:0] col;
wire[3:0] row;
reg reset,clk;
reg[15:0] key;
integer j,k;
reg[39;0] pressed;
parameter [39:0] key_0="key_0";
parameter [39:0] key_1="key_1";

parameter [39:0] key_2="key_2";
parameter [39:0] key_3="key_3";
parameter [39:0] key_4="key_4";
parameter [39:0] key_5="key_5";
parameter [39:0] key_6="key_6";
parameter [39:0] key_7="key_7";
parameter [39:0] key_8="key_8";
parameter [39:0] key_9="key_9";
parameter [39:0] key_A="key_A";
parameter [39:0] key_B="key_B";
parameter [39:0] key_C="key_C";
parameter [39:0] key_D="key_D";
parameter [39:0] key_E="key_E";
parameter [39:0] key_F="key_F";
parameter [39:0] none="none";

always @(key)
16'h0000: pressed=none;
16'h0001: pressed=key_0;
16'h0002: pressed=key_1;
16'h0004: pressed=key_2;
16'h0008: pressed=key_3;

16'h0010: pressed=key_4;
16'h0020: pressed=key_5;
16'h0040: pressed=key_6;
16'h0080: pressed=key_7;

16'h0100: pressed=key_8;
16'h0200: pressed=key_9;
16'h0400: pressed=key_A;
16'h0800: pressed=key_B;

16'h1000: pressed=key_C;
16'h2000: pressed=key_D;
16'h4000: pressed=key_E;


16'h8000 pressed=key_F;
default:pressed=none;
endcase
end
keyboard m0(code,col,valid,row,s_row,clk,reset);
row_signal m1(row,key,col);
sychn m3(s_row,ro,clk,reset);
initial #2000 $finish;
initial begin clk=0;
forever #5 clk=~clk;
end
initial
begin
for(k=0;k<=1;k=k+1)
begin
key=0;
#20
for(j=0;j<=16;j=j+1)
begin
#20 key[j]=1;
#60 key=0
end
end
end
endmodule