📄 keyboard.map.rpt
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Analysis & Synthesis report for keyboard
Sat Oct 27 01:04:25 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Failed - Sat Oct 27 01:04:25 2007 ;
; Quartus II Version ; 6.1 Build 201 11/27/2006 SJ Full Version ;
; Revision Name ; keyboard ;
; Top-level Entity Name ; keyboard ;
; Family ; Stratix II ;
; Logic utilization ; N/A until Partition Merge ;
; Combinational ALUTs ; N/A until Partition Merge ;
; Dedicated logic registers ; N/A until Partition Merge ;
; Total registers ; N/A until Partition Merge ;
; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; N/A until Partition Merge ;
; Total block memory bits ; N/A until Partition Merge ;
; DSP block 9-bit elements ; N/A until Partition Merge ;
; Total PLLs ; N/A until Partition Merge ;
; Total DLLs ; N/A until Partition Merge ;
+-------------------------------+------------------------------------------+
+----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------+--------------------+--------------------+
; Device ; EP2S15F484C3 ; ;
; Top-level entity name ; keyboard ; keyboard ;
; Family name ; Stratix II ; Stratix ;
; Type of Retiming Performed During Resynthesis ; Full ; ;
; Resynthesis Optimization Effort ; Normal ; ;
; Physical Synthesis Level for Resynthesis ; Normal ; ;
; Use Generated Physical Constraints File ; On ; ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Stratix II/Stratix III ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix II/Stratix III ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Use smart compilation ; Off ; Off ;
+----------------------------------------------------------+--------------------+--------------------+
+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Sat Oct 27 01:04:23 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off keyboard -c keyboard
Critical Warning (10226): Verilog HDL Port Declaration warning at keyboard.v(3): port declaration for "col" declares packed dimensions but the data type declaration does not
Info (10151): Verilog HDL Declaration information at keyboard.v(7): "col" is declared here
Critical Warning (10226): Verilog HDL Port Declaration warning at keyboard.v(5): port declaration for "code" declares packed dimensions but the data type declaration does not
Info (10151): Verilog HDL Declaration information at keyboard.v(7): "code" is declared here
Critical Warning (10226): Verilog HDL Port Declaration warning at keyboard.v(72): port declaration for "row" declares packed dimensions but the data type declaration does not
Info (10151): Verilog HDL Declaration information at keyboard.v(75): "row" is declared here
Info: Found 3 design units, including 3 entities, in source file keyboard.v
Info: Found entity 1: keyboard
Info: Found entity 2: synch
Info: Found entity 3: row_signal
Error (10053): Verilog HDL error at keyboard.v(78): variable "row" cannot be indexed because it is not declared as an array File: D:/keyboard/keyboard.v Line: 78
Error (10053): Verilog HDL error at keyboard.v(79): variable "row" cannot be indexed because it is not declared as an array File: D:/keyboard/keyboard.v Line: 79
Error (10053): Verilog HDL error at keyboard.v(80): variable "row" cannot be indexed because it is not declared as an array File: D:/keyboard/keyboard.v Line: 80
Error (10053): Verilog HDL error at keyboard.v(81): variable "row" cannot be indexed because it is not declared as an array File: D:/keyboard/keyboard.v Line: 81
Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 3 warnings
Info: Allocated 120 megabytes of memory during processing
Error: Processing ended: Sat Oct 27 01:04:25 2007
Error: Elapsed time: 00:00:02
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