gray_counter.fit.smsg

gray码计数器 用于减少出错率 代码已经仿真 请放心下载

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Mon Oct 22 19:04:48 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off gray_counter -c gray_counter
Info: Selected device EP2C5F256C6 for design "gray_counter"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 16 of 16 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C8F256C6 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location C3
    Info: Pin ~nCSO~ is reserved at location F4
    Info: Pin ~LVDS41p/nCEO~ is reserved at location N14
Warning: No exact pin location assignment(s) for 8 pins of 8 total pins
    Info: Pin q[3] not assigned to an exact location on the device
    Info: Pin q[2] not assigned to an exact location on the device
    Info: Pin q[1] not assigned to an exact location on the device
    Info: Pin qb[3] not assigned to an exact location on the device
    Info: Pin qb[2] not assigned to an exact location on the device
    Info: Pin qb[1] not assigned to an exact location on the device
    Info: Pin clr not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Automatically promoted node clk (placed in PIN H2 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 7 (unused VREF, 3.30 VCCIO, 1 input, 6 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  32 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  43 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  38 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  41 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 0.707 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X1_Y4; Fanout = 4; REG Node = 'counter[3]'
    Info: 2: + IC(0.473 ns) + CELL(0.150 ns) = 0.623 ns; Loc. = LAB_X1_Y4; Fanout = 1; COMB Node = 'counter~55'
    Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.707 ns; Loc. = LAB_X1_Y4; Fanout = 4; REG Node = 'counter[2]'
    Info: Total cell delay = 0.234 ns ( 33.10 % )
    Info: Total interconnect delay = 0.473 ns ( 66.90 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y0 to location X13_Y14
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 6 output pins without output pin load capacitance assignment
    Info: Pin "q[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "q[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "q[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qb[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qb[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "qb[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 169 megabytes of memory during processing
    Info: Processing ended: Mon Oct 22 19:04:55 2007
    Info: Elapsed time: 00:00:07