gray_counter.v

来自「gray码计数器 用于减少出错率 代码已经仿真 请放心下载」· Verilog 代码 · 共 21 行

module gray_counter(clk,clr,q,qb);
parameter bits=3;
input clk,clr;
output[1:bits] q,qb;
//reg [1:bits] q,qb;
reg[1:bits] counter,grayout;
integer k;
always @(posedge clk)
begin
if(!clr) counter<=0;
else counter<=counter+1;
end
always@(counter)
begin
grayout[1]=counter[1];
for(k=2;k<=bits;k=k+1)
grayout[k]=counter[k]^counter[k-1];
end
assign q=grayout;
assign qb=~grayout;
endmodule