📄 gray_counter.tan.qmsg

📁 gray码计数器用于减少出错率代码已经仿真请放心下载
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register counter\[2\] counter\[1\] 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"counter\[2\]\" and destination register \"counter\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.855 ns + Longest register register " "Info: + Longest register to register delay is 0.855 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[2\] 1 REG LCFF_X1_Y4_N13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y4_N13; Fanout = 4; REG Node = 'counter\[2\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[2] } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.334 ns) + CELL(0.437 ns) 0.771 ns counter~57 2 COMB LCCOMB_X1_Y4_N0 1 " "Info: 2: + IC(0.334 ns) + CELL(0.437 ns) = 0.771 ns; Loc. = LCCOMB_X1_Y4_N0; Fanout = 1; COMB Node = 'counter~57'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.771 ns" { counter[2] counter~57 } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.855 ns counter\[1\] 3 REG LCFF_X1_Y4_N1 4 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.855 ns; Loc. = LCFF_X1_Y4_N1; Fanout = 4; REG Node = 'counter\[1\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { counter~57 counter[1] } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.521 ns ( 60.94 % ) " "Info: Total cell delay = 0.521 ns ( 60.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.334 ns ( 39.06 % ) " "Info: Total interconnect delay = 0.334 ns ( 39.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.855 ns" { counter[2] counter~57 counter[1] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.855 ns" { counter[2] counter~57 counter[1] } { 0.000ns 0.334ns 0.000ns } { 0.000ns 0.437ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.339 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.339 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 3 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 2.339 ns counter\[1\] 3 REG LCFF_X1_Y4_N1 4 " "Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.339 ns; Loc. = LCFF_X1_Y4_N1; Fanout = 4; REG Node = 'counter\[1\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.238 ns" { clk~clkctrl counter[1] } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.81 % ) " "Info: Total cell delay = 1.516 ns ( 64.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 35.19 % ) " "Info: Total interconnect delay = 0.823 ns ( 35.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clk clk~clkctrl counter[1] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clk clk~combout clk~clkctrl counter[1] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.339 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.339 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 3 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 2.339 ns counter\[2\] 3 REG LCFF_X1_Y4_N13 4 " "Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.339 ns; Loc. = LCFF_X1_Y4_N13; Fanout = 4; REG Node = 'counter\[2\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.238 ns" { clk~clkctrl counter[2] } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.81 % ) " "Info: Total cell delay = 1.516 ns ( 64.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 35.19 % ) " "Info: Total interconnect delay = 0.823 ns ( 35.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clk clk~clkctrl counter[2] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clk clk~combout clk~clkctrl counter[2] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clk clk~clkctrl counter[1] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clk clk~combout clk~clkctrl counter[1] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clk clk~clkctrl counter[2] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clk clk~combout clk~clkctrl counter[2] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.855 ns" { counter[2] counter~57 counter[1] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.855 ns" { counter[2] counter~57 counter[1] } { 0.000ns 0.334ns 0.000ns } { 0.000ns 0.437ns 0.084ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clk clk~clkctrl counter[1] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clk clk~combout clk~clkctrl counter[1] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clk clk~clkctrl counter[2] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clk clk~combout clk~clkctrl counter[2] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[1] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { counter[1] } {  } {  } "" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "counter\[1\] clr clk 3.739 ns register " "Info: tsu for register \"counter\[1\]\" (data pin = \"clr\", clock pin = \"clk\") is 3.739 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.114 ns + Longest pin register " "Info: + Longest pin to register delay is 6.114 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.822 ns) 0.822 ns clr 1 PIN PIN_K5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.822 ns) = 0.822 ns; Loc. = PIN_K5; Fanout = 3; PIN Node = 'clr'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.789 ns) + CELL(0.419 ns) 6.030 ns counter~57 2 COMB LCCOMB_X1_Y4_N0 1 " "Info: 2: + IC(4.789 ns) + CELL(0.419 ns) = 6.030 ns; Loc. = LCCOMB_X1_Y4_N0; Fanout = 1; COMB Node = 'counter~57'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.208 ns" { clr counter~57 } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.114 ns counter\[1\] 3 REG LCFF_X1_Y4_N1 4 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.114 ns; Loc. = LCFF_X1_Y4_N1; Fanout = 4; REG Node = 'counter\[1\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { counter~57 counter[1] } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.325 ns ( 21.67 % ) " "Info: Total cell delay = 1.325 ns ( 21.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.789 ns ( 78.33 % ) " "Info: Total interconnect delay = 4.789 ns ( 78.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.114 ns" { clr counter~57 counter[1] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.114 ns" { clr clr~combout counter~57 counter[1] } { 0.000ns 0.000ns 4.789ns 0.000ns } { 0.000ns 0.822ns 0.419ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.339 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.339 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 3 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 2.339 ns counter\[1\] 3 REG LCFF_X1_Y4_N1 4 " "Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.339 ns; Loc. = LCFF_X1_Y4_N1; Fanout = 4; REG Node = 'counter\[1\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.238 ns" { clk~clkctrl counter[1] } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.81 % ) " "Info: Total cell delay = 1.516 ns ( 64.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 35.19 % ) " "Info: Total interconnect delay = 0.823 ns ( 35.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clk clk~clkctrl counter[1] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clk clk~combout clk~clkctrl counter[1] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.114 ns" { clr counter~57 counter[1] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.114 ns" { clr clr~combout counter~57 counter[1] } { 0.000ns 0.000ns 4.789ns 0.000ns } { 0.000ns 0.822ns 0.419ns 0.084ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clk clk~clkctrl counter[1] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clk clk~combout clk~clkctrl counter[1] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk qb\[3\] counter\[3\] 6.581 ns register " "Info: tco from clock \"clk\" to destination pin \"qb\[3\]\" through register \"counter\[3\]\" is 6.581 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.339 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.339 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 3 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 2.339 ns counter\[3\] 3 REG LCFF_X1_Y4_N7 4 " "Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.339 ns; Loc. = LCFF_X1_Y4_N7; Fanout = 4; REG Node = 'counter\[3\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.238 ns" { clk~clkctrl counter[3] } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.81 % ) " "Info: Total cell delay = 1.516 ns ( 64.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 35.19 % ) " "Info: Total interconnect delay = 0.823 ns ( 35.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clk clk~clkctrl counter[3] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clk clk~combout clk~clkctrl counter[3] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.992 ns + Longest register pin " "Info: + Longest register to pin delay is 3.992 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[3\] 1 REG LCFF_X1_Y4_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y4_N7; Fanout = 4; REG Node = 'counter\[3\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[3] } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.491 ns) + CELL(0.420 ns) 0.911 ns grayout~1 2 COMB LCCOMB_X1_Y4_N20 2 " "Info: 2: + IC(0.491 ns) + CELL(0.420 ns) = 0.911 ns; Loc. = LCCOMB_X1_Y4_N20; Fanout = 2; COMB Node = 'grayout~1'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.911 ns" { counter[3] grayout~1 } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.459 ns) + CELL(2.622 ns) 3.992 ns qb\[3\] 3 PIN PIN_M2 0 " "Info: 3: + IC(0.459 ns) + CELL(2.622 ns) = 3.992 ns; Loc. = PIN_M2; Fanout = 0; PIN Node = 'qb\[3\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.081 ns" { grayout~1 qb[3] } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.042 ns ( 76.20 % ) " "Info: Total cell delay = 3.042 ns ( 76.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.950 ns ( 23.80 % ) " "Info: Total interconnect delay = 0.950 ns ( 23.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.992 ns" { counter[3] grayout~1 qb[3] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.992 ns" { counter[3] grayout~1 qb[3] } { 0.000ns 0.491ns 0.459ns } { 0.000ns 0.420ns 2.622ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clk clk~clkctrl counter[3] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clk clk~combout clk~clkctrl counter[3] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.992 ns" { counter[3] grayout~1 qb[3] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.992 ns" { counter[3] grayout~1 qb[3] } { 0.000ns 0.491ns 0.459ns } { 0.000ns 0.420ns 2.622ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "counter\[3\] clr clk -3.235 ns register " "Info: th for register \"counter\[3\]\" (data pin = \"clr\", clock pin = \"clk\") is -3.235 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.339 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.339 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 3 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 2.339 ns counter\[3\] 3 REG LCFF_X1_Y4_N7 4 " "Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.339 ns; Loc. = LCFF_X1_Y4_N7; Fanout = 4; REG Node = 'counter\[3\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.238 ns" { clk~clkctrl counter[3] } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.81 % ) " "Info: Total cell delay = 1.516 ns ( 64.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 35.19 % ) " "Info: Total interconnect delay = 0.823 ns ( 35.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clk clk~clkctrl counter[3] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clk clk~combout clk~clkctrl counter[3] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.840 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.822 ns) 0.822 ns clr 1 PIN PIN_K5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.822 ns) = 0.822 ns; Loc. = PIN_K5; Fanout = 3; PIN Node = 'clr'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.784 ns) + CELL(0.150 ns) 5.756 ns counter~56 2 COMB LCCOMB_X1_Y4_N6 1 " "Info: 2: + IC(4.784 ns) + CELL(0.150 ns) = 5.756 ns; Loc. = LCCOMB_X1_Y4_N6; Fanout = 1; COMB Node = 'counter~56'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.934 ns" { clr counter~56 } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 5.840 ns counter\[3\] 3 REG LCFF_X1_Y4_N7 4 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 5.840 ns; Loc. = LCFF_X1_Y4_N7; Fanout = 4; REG Node = 'counter\[3\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { counter~56 counter[3] } "NODE_NAME" } } { "gray_counter.v" "" { Text "D:/iii/gray_counter.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.056 ns ( 18.08 % ) " "Info: Total cell delay = 1.056 ns ( 18.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.784 ns ( 81.92 % ) " "Info: Total interconnect delay = 4.784 ns ( 81.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.840 ns" { clr counter~56 counter[3] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.840 ns" { clr clr~combout counter~56 counter[3] } { 0.000ns 0.000ns 4.784ns 0.000ns } { 0.000ns 0.822ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clk clk~clkctrl counter[3] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clk clk~combout clk~clkctrl counter[3] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.840 ns" { clr counter~56 counter[3] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.840 ns" { clr clr~combout counter~56 counter[3] } { 0.000ns 0.000ns 4.784ns 0.000ns } { 0.000ns 0.822ns 0.150ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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