gray_counter.vo

gray码计数器 用于减少出错率 代码已经仿真 请放心下载

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.1 Build 201 11/27/2006 SJ Full Version"

// DATE "10/22/2007 19:05:12"

// 
// Device: Altera EP2C5F256C6 Package FBGA256
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module gray_counter (
	clk,
	clr,
	q,
	qb);
input 	clk;
input 	clr;
output 	[3:1] q;
output 	[3:1] qb;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("gray_counter_v.sdo");
// synopsys translate_on

wire \clk~combout ;
wire \clk~clkctrl ;
wire \clr~combout ;
wire \counter~56 ;
wire \counter~55 ;
wire \grayout~1 ;
wire \counter~57 ;
wire \grayout~0 ;
wire [1:3] counter;


// atom is at PIN_H2
cycloneii_io \clk~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(clk));
// synopsys translate_off
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .oe_power_up = "low";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .operation_mode = "input";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at CLKCTRL_G2
cycloneii_clkctrl \clk~clkctrl_I (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\clk~combout }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\clk~clkctrl ));
// synopsys translate_off
defparam \clk~clkctrl_I .clock_type = "global clock";
defparam \clk~clkctrl_I .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at PIN_K5
cycloneii_io \clr~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clr~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(clr));
// synopsys translate_off
defparam \clr~I .input_async_reset = "none";
defparam \clr~I .input_power_up = "low";
defparam \clr~I .input_register_mode = "none";
defparam \clr~I .input_sync_reset = "none";
defparam \clr~I .oe_async_reset = "none";
defparam \clr~I .oe_power_up = "low";
defparam \clr~I .oe_register_mode = "none";
defparam \clr~I .oe_sync_reset = "none";
defparam \clr~I .operation_mode = "input";
defparam \clr~I .output_async_reset = "none";
defparam \clr~I .output_power_up = "low";
defparam \clr~I .output_register_mode = "none";
defparam \clr~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCCOMB_X1_Y4_N6
cycloneii_lcell_comb \counter~56_I (
// Equation(s):
// \counter~56  = !counter[3] & \clr~combout 

	.dataa(vcc),
	.datab(vcc),
	.datac(counter[3]),
	.datad(\clr~combout ),
	.cin(gnd),
	.combout(\counter~56 ),
	.cout());
// synopsys translate_off
defparam \counter~56_I .lut_mask = 16'h0F00;
defparam \counter~56_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCFF_X1_Y4_N7
cycloneii_lcell_ff \counter[3]~I (
	.clk(\clk~clkctrl ),
	.datain(\counter~56 ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(counter[3]));

// atom is at LCCOMB_X1_Y4_N12
cycloneii_lcell_comb \counter~55_I (
// Equation(s):
// \counter~55  = \clr~combout  & (counter[2] $ counter[3])

	.dataa(vcc),
	.datab(\clr~combout ),
	.datac(counter[2]),
	.datad(counter[3]),
	.cin(gnd),
	.combout(\counter~55 ),
	.cout());
// synopsys translate_off
defparam \counter~55_I .lut_mask = 16'h0CC0;
defparam \counter~55_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCFF_X1_Y4_N13
cycloneii_lcell_ff \counter[2]~I (
	.clk(\clk~clkctrl ),
	.datain(\counter~55 ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(counter[2]));

// atom is at LCCOMB_X1_Y4_N20
cycloneii_lcell_comb \grayout~1_I (
// Equation(s):
// \grayout~1  = counter[3] $ counter[2]

	.dataa(vcc),
	.datab(counter[3]),
	.datac(counter[2]),
	.datad(vcc),
	.cin(gnd),
	.combout(\grayout~1 ),
	.cout());
// synopsys translate_off
defparam \grayout~1_I .lut_mask = 16'h3C3C;
defparam \grayout~1_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X1_Y4_N0
cycloneii_lcell_comb \counter~57_I (
// Equation(s):
// \counter~57  = \clr~combout  & (counter[1] $ (counter[2] & counter[3]))

	.dataa(counter[2]),
	.datab(\clr~combout ),
	.datac(counter[1]),
	.datad(counter[3]),
	.cin(gnd),
	.combout(\counter~57 ),
	.cout());
// synopsys translate_off
defparam \counter~57_I .lut_mask = 16'h48C0;
defparam \counter~57_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCFF_X1_Y4_N1
cycloneii_lcell_ff \counter[1]~I (
	.clk(\clk~clkctrl ),
	.datain(\counter~57 ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(counter[1]));

// atom is at LCCOMB_X1_Y4_N28
cycloneii_lcell_comb \grayout~0_I (
// Equation(s):
// \grayout~0  = counter[2] $ counter[1]

	.dataa(vcc),
	.datab(vcc),
	.datac(counter[2]),
	.datad(counter[1]),
	.cin(gnd),
	.combout(\grayout~0 ),
	.cout());
// synopsys translate_off
defparam \grayout~0_I .lut_mask = 16'h0FF0;
defparam \grayout~0_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at PIN_L1
cycloneii_io \q[3]~I (
	.datain(\grayout~1 ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(q[3]));
// synopsys translate_off
defparam \q[3]~I .input_async_reset = "none";
defparam \q[3]~I .input_power_up = "low";
defparam \q[3]~I .input_register_mode = "none";
defparam \q[3]~I .input_sync_reset = "none";
defparam \q[3]~I .oe_async_reset = "none";
defparam \q[3]~I .oe_power_up = "low";
defparam \q[3]~I .oe_register_mode = "none";
defparam \q[3]~I .oe_sync_reset = "none";
defparam \q[3]~I .operation_mode = "output";
defparam \q[3]~I .output_async_reset = "none";
defparam \q[3]~I .output_power_up = "low";
defparam \q[3]~I .output_register_mode = "none";
defparam \q[3]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_M1
cycloneii_io \q[2]~I (
	.datain(\grayout~0 ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(q[2]));
// synopsys translate_off
defparam \q[2]~I .input_async_reset = "none";
defparam \q[2]~I .input_power_up = "low";
defparam \q[2]~I .input_register_mode = "none";
defparam \q[2]~I .input_sync_reset = "none";
defparam \q[2]~I .oe_async_reset = "none";
defparam \q[2]~I .oe_power_up = "low";
defparam \q[2]~I .oe_register_mode = "none";
defparam \q[2]~I .oe_sync_reset = "none";
defparam \q[2]~I .operation_mode = "output";
defparam \q[2]~I .output_async_reset = "none";
defparam \q[2]~I .output_power_up = "low";
defparam \q[2]~I .output_register_mode = "none";
defparam \q[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_K2
cycloneii_io \q[1]~I (
	.datain(counter[1]),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(q[1]));
// synopsys translate_off
defparam \q[1]~I .input_async_reset = "none";
defparam \q[1]~I .input_power_up = "low";
defparam \q[1]~I .input_register_mode = "none";
defparam \q[1]~I .input_sync_reset = "none";
defparam \q[1]~I .oe_async_reset = "none";
defparam \q[1]~I .oe_power_up = "low";
defparam \q[1]~I .oe_register_mode = "none";
defparam \q[1]~I .oe_sync_reset = "none";
defparam \q[1]~I .operation_mode = "output";
defparam \q[1]~I .output_async_reset = "none";
defparam \q[1]~I .output_power_up = "low";
defparam \q[1]~I .output_register_mode = "none";
defparam \q[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_M2
cycloneii_io \qb[3]~I (
	.datain(!\grayout~1 ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(qb[3]));
// synopsys translate_off
defparam \qb[3]~I .input_async_reset = "none";
defparam \qb[3]~I .input_power_up = "low";
defparam \qb[3]~I .input_register_mode = "none";
defparam \qb[3]~I .input_sync_reset = "none";
defparam \qb[3]~I .oe_async_reset = "none";
defparam \qb[3]~I .oe_power_up = "low";
defparam \qb[3]~I .oe_register_mode = "none";
defparam \qb[3]~I .oe_sync_reset = "none";
defparam \qb[3]~I .operation_mode = "output";
defparam \qb[3]~I .output_async_reset = "none";
defparam \qb[3]~I .output_power_up = "low";
defparam \qb[3]~I .output_register_mode = "none";
defparam \qb[3]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_J4
cycloneii_io \qb[2]~I (
	.datain(!\grayout~0 ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(qb[2]));
// synopsys translate_off
defparam \qb[2]~I .input_async_reset = "none";
defparam \qb[2]~I .input_power_up = "low";
defparam \qb[2]~I .input_register_mode = "none";
defparam \qb[2]~I .input_sync_reset = "none";
defparam \qb[2]~I .oe_async_reset = "none";
defparam \qb[2]~I .oe_power_up = "low";
defparam \qb[2]~I .oe_register_mode = "none";
defparam \qb[2]~I .oe_sync_reset = "none";
defparam \qb[2]~I .operation_mode = "output";
defparam \qb[2]~I .output_async_reset = "none";
defparam \qb[2]~I .output_power_up = "low";
defparam \qb[2]~I .output_register_mode = "none";
defparam \qb[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_K4
cycloneii_io \qb[1]~I (
	.datain(!counter[1]),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(qb[1]));
// synopsys translate_off
defparam \qb[1]~I .input_async_reset = "none";
defparam \qb[1]~I .input_power_up = "low";
defparam \qb[1]~I .input_register_mode = "none";
defparam \qb[1]~I .input_sync_reset = "none";
defparam \qb[1]~I .oe_async_reset = "none";
defparam \qb[1]~I .oe_power_up = "low";
defparam \qb[1]~I .oe_register_mode = "none";
defparam \qb[1]~I .oe_sync_reset = "none";
defparam \qb[1]~I .operation_mode = "output";
defparam \qb[1]~I .output_async_reset = "none";
defparam \qb[1]~I .output_power_up = "low";
defparam \qb[1]~I .output_register_mode = "none";
defparam \qb[1]~I .output_sync_reset = "none";
// synopsys translate_on

endmodule