gray_counter.tan.rpt

gray码计数器 用于减少出错率 代码已经仿真 请放心下载

+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To    ; From Clock ;
+-------+--------------+------------+------------+-------+------------+
; N/A   ; None         ; 6.581 ns   ; counter[3] ; qb[3] ; clk        ;
; N/A   ; None         ; 6.571 ns   ; counter[3] ; q[3]  ; clk        ;
; N/A   ; None         ; 6.452 ns   ; counter[2] ; qb[3] ; clk        ;
; N/A   ; None         ; 6.449 ns   ; counter[2] ; q[2]  ; clk        ;
; N/A   ; None         ; 6.442 ns   ; counter[2] ; q[3]  ; clk        ;
; N/A   ; None         ; 6.429 ns   ; counter[2] ; qb[2] ; clk        ;
; N/A   ; None         ; 6.140 ns   ; counter[1] ; q[2]  ; clk        ;
; N/A   ; None         ; 6.120 ns   ; counter[1] ; qb[2] ; clk        ;
; N/A   ; None         ; 5.890 ns   ; counter[1] ; qb[1] ; clk        ;
; N/A   ; None         ; 5.890 ns   ; counter[1] ; q[1]  ; clk        ;
+-------+--------------+------------+------------+-------+------------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To         ; To Clock ;
+---------------+-------------+-----------+------+------------+----------+
; N/A           ; None        ; -3.235 ns ; clr  ; counter[3] ; clk      ;
; N/A           ; None        ; -3.506 ns ; clr  ; counter[2] ; clk      ;
; N/A           ; None        ; -3.509 ns ; clr  ; counter[1] ; clk      ;
+---------------+-------------+-----------+------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Mon Oct 22 19:05:08 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off gray_counter -c gray_counter --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "counter[2]" and destination register "counter[1]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.855 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y4_N13; Fanout = 4; REG Node = 'counter[2]'
            Info: 2: + IC(0.334 ns) + CELL(0.437 ns) = 0.771 ns; Loc. = LCCOMB_X1_Y4_N0; Fanout = 1; COMB Node = 'counter~57'
            Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.855 ns; Loc. = LCFF_X1_Y4_N1; Fanout = 4; REG Node = 'counter[1]'
            Info: Total cell delay = 0.521 ns ( 60.94 % )
            Info: Total interconnect delay = 0.334 ns ( 39.06 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.339 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.339 ns; Loc. = LCFF_X1_Y4_N1; Fanout = 4; REG Node = 'counter[1]'
                Info: Total cell delay = 1.516 ns ( 64.81 % )
                Info: Total interconnect delay = 0.823 ns ( 35.19 % )
            Info: - Longest clock path from clock "clk" to source register is 2.339 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.339 ns; Loc. = LCFF_X1_Y4_N13; Fanout = 4; REG Node = 'counter[2]'
                Info: Total cell delay = 1.516 ns ( 64.81 % )
                Info: Total interconnect delay = 0.823 ns ( 35.19 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "counter[1]" (data pin = "clr", clock pin = "clk") is 3.739 ns
    Info: + Longest pin to register delay is 6.114 ns
        Info: 1: + IC(0.000 ns) + CELL(0.822 ns) = 0.822 ns; Loc. = PIN_K5; Fanout = 3; PIN Node = 'clr'
        Info: 2: + IC(4.789 ns) + CELL(0.419 ns) = 6.030 ns; Loc. = LCCOMB_X1_Y4_N0; Fanout = 1; COMB Node = 'counter~57'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.114 ns; Loc. = LCFF_X1_Y4_N1; Fanout = 4; REG Node = 'counter[1]'
        Info: Total cell delay = 1.325 ns ( 21.67 % )
        Info: Total interconnect delay = 4.789 ns ( 78.33 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.339 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.339 ns; Loc. = LCFF_X1_Y4_N1; Fanout = 4; REG Node = 'counter[1]'
        Info: Total cell delay = 1.516 ns ( 64.81 % )
        Info: Total interconnect delay = 0.823 ns ( 35.19 % )
Info: tco from clock "clk" to destination pin "qb[3]" through register "counter[3]" is 6.581 ns
    Info: + Longest clock path from clock "clk" to source register is 2.339 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.339 ns; Loc. = LCFF_X1_Y4_N7; Fanout = 4; REG Node = 'counter[3]'
        Info: Total cell delay = 1.516 ns ( 64.81 % )
        Info: Total interconnect delay = 0.823 ns ( 35.19 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.992 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y4_N7; Fanout = 4; REG Node = 'counter[3]'
        Info: 2: + IC(0.491 ns) + CELL(0.420 ns) = 0.911 ns; Loc. = LCCOMB_X1_Y4_N20; Fanout = 2; COMB Node = 'grayout~1'
        Info: 3: + IC(0.459 ns) + CELL(2.622 ns) = 3.992 ns; Loc. = PIN_M2; Fanout = 0; PIN Node = 'qb[3]'
        Info: Total cell delay = 3.042 ns ( 76.20 % )
        Info: Total interconnect delay = 0.950 ns ( 23.80 % )
Info: th for register "counter[3]" (data pin = "clr", clock pin = "clk") is -3.235 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.339 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.339 ns; Loc. = LCFF_X1_Y4_N7; Fanout = 4; REG Node = 'counter[3]'
        Info: Total cell delay = 1.516 ns ( 64.81 % )
        Info: Total interconnect delay = 0.823 ns ( 35.19 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 5.840 ns
        Info: 1: + IC(0.000 ns) + CELL(0.822 ns) = 0.822 ns; Loc. = PIN_K5; Fanout = 3; PIN Node = 'clr'
        Info: 2: + IC(4.784 ns) + CELL(0.150 ns) = 5.756 ns; Loc. = LCCOMB_X1_Y4_N6; Fanout = 1; COMB Node = 'counter~56'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 5.840 ns; Loc. = LCFF_X1_Y4_N7; Fanout = 4; REG Node = 'counter[3]'
        Info: Total cell delay = 1.056 ns ( 18.08 % )
        Info: Total interconnect delay = 4.784 ns ( 81.92 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 102 megabytes of memory during processing
    Info: Processing ended: Mon Oct 22 19:05:09 2007
    Info: Elapsed time: 00:00:01