pc.v

来自「：首先介绍了DS--UWB系统的的发射与接收模型」· Verilog 代码 · 共 100 行

//--------------------------------------------------------------------------------
// Module    : decode.v
// File Name :
// Version   : 1.0
// Date      :
// Author    :
// Modify    :
// Function  :
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
`include "./define/define.h"
                                                                                                                                    
module pc_8051(
    clock,
    reset,
                                                                                                                                    
    fsm_state,
    fsm_pc_cnt,
    fsm_pc_num,
    
    pc_we,
    pc_jump,
    pc_wdata,

    pc_out,

    pc_reg
);

//--------------------------------------------------------------------------------
// Interface declarations
//--------------------------------------------------------------------------------
    input         clock;
    input         reset;
                                                                                                                                    
    input  [2:0]  fsm_state;
    input  [1:0]  fsm_pc_cnt;
    input  [1:0]  fsm_pc_num;
    
    input         pc_we;
    input         pc_jump;
    input  [15:0] pc_wdata;

    output [15:0] pc_out;

    output [15:0] pc_reg;

//--------------------------------------------------------------------------------
// Interface signal declarations
//--------------------------------------------------------------------------------
    wire        clock;
    wire        reset;
                                                                                                                                    
    wire [2:0]  fsm_state;
    wire [1:0]  fsm_pc_cnt;
    wire [1:0]  fsm_pc_num;
    
    wire        pc_we;
    wire        pc_jump;
    wire [15:0] pc_wdata;

    wire [15:0] pc_out;

    wire [15:0] pc_reg;

//--------------------------------------------------------------------------------
// Internal signal declarations
//--------------------------------------------------------------------------------
    reg   [15:0] pc;

    reg   [15:0] pc_out_val;

//--------------------------------------------------------------------------------
// Main function 
//--------------------------------------------------------------------------------
    always@(posedge clock or posedge reset)
    begin
        if (reset) begin
            pc <=0;
        end else if (fsm_state == `WRITE_BACK) begin
            if      (pc_we &  pc_jump) pc <= pc_wdata + fsm_pc_num;
            else if (pc_we & ~pc_jump) pc <= pc_wdata;
            else                       pc <= pc       + fsm_pc_num;
        end
    end
    assign pc_reg = pc;

    always @(fsm_state or fsm_pc_cnt or pc)
    begin
        if (fsm_state == `FETCH) begin
            pc_out_val = pc + fsm_pc_cnt + 1;
        end else begin
            pc_out_val = pc;
        end
    end
    assign pc_out = pc_out_val;

endmodule