fsm8051.v

：首先介绍了DS--UWB系统的的发射与接收模型

//--------------------------------------------------------------------------------
// Module    : fsm8051.v
// File Name :
// Version   : 1.0
// Date      :
// Author    :
// Modify    :
// Function  :
//--------------------------------------------------------------------------------
`timescale 1ns/1ns

module fsm8051(
    clock,
    reset,

    fsm8051_inst_in,

    fsm8051_inst_out,
    fsm8051_state_out
);

//--------------------------------------------------------------------------------
// Interface declarations
//--------------------------------------------------------------------------------
    input         clock;
    input         reset;

    input  [7:0]  fsm8051_inst_in;
 
//--------------------------------------------------------------------------------
// Interface declarations
//--------------------------------------------------------------------------------
    wire         clock;
    wire         reset;

    wire  [23:0] fsm8051_inst_in;
 
//--------------------------------------------------------------------------------
//  Internal signal declarations
//--------------------------------------------------------------------------------
    wire  [23:0] fsm8051_inst;

//--------------------------------------------------------------------------------
//  Internal register signal declarations
//--------------------------------------------------------------------------------
    reg  [23:0] inst_reg;

//--------------------------------------------------------------------------------
//  Parameter declarations 
//--------------------------------------------------------------------------------
    parameter IDLE = 0, FETCH = 1, DECODE = 2, READING = 3, EXECUTION = 4, WRITE_BACK = 5;

//--------------------------------------------------------------------------------
//  Main declarations
//--------------------------------------------------------------------------------

    always @(posedge clock or posedge reset)
    begin
        if (reset) begin
            state_8051 <= 0;
        end else case (state_8051)
            IDLE      : state <= FETCH;
            FETCH     : begin
                if (inst_num == inst_num_cnt) state <= DECODE;
                else                          state <= FETCH;
            end
            DECODE    : state <= READING;
            READING   : state <= EXECUTION;
            EXECUTION : begin
                if (fsm8051_execEnd_in) state <= WRITE_BACK;
                else                    state <= EXECUTION;
            end
            WRITE_BACK: state <= IDLE;
            default   : state <= IDLE;
        end
    end
    assign fsm8051_state_out = state;

    always @(posedge clock or posedge reset)
    begin
        if (reset) begin
            inst_num_cnt <= 0;
        end else if (state_8051 == FETCH) begin
            inst_num_cnt <= inst_num_cnt + 1;
        end else begin
            inst_num_cnt <= 0;
        end
    end
    assign fsm8051_pcCnt_out = inst_num_cnt;
            
    always @(fsm8051_inst_in)
    begin
        casex (fsm8051_inst_in)
            OC8051_INC_R : inst_num = 0; 
            OC8051_INC_I : inst_num = 0; 
            OC8051_INC_A : begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = IMMD_VAL; end
            OC8051_INC_D : begin aluctl = ADD_OPR;    first_opr = INT_MEM;   second_opr = IMMD_VAL; end
            OC8051_RR    : begin aluctl = SHF_RR_OPR; first_opr = ACC_MEM;   second_opr = NONE_VAL; end
            OC8051_LJMP  : begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end 

            OC8051_DEC_R : begin aluctl = ADD_OPR;    first_opr = REG_GROUP; second_opr = IMMD_VAL; end
            OC8051_DEC_I : begin aluctl = ADD_OPR;    first_opr = INT_MEM;   second_opr = IMMD_VAL; end
            OC8051_DEC_A : begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = IMMD_VAL; end
            OC8051_DEC_D : begin aluctl = ADD_OPR;    first_opr = INT_MEM;   second_opr = IMMD_VAL; end
            OC8051_RRC   : begin aluctl = SHF_RRC_OPR;first_opr = ACC_MEM;   second_opr = NONE_VAL; end
            OC8051_LCALL : begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end

            OC8051_ADD_R : begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = REG_GROUP;end 
            OC8051_ADD_I : begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end 
            OC8051_ADD_D : begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end 
            OC8051_ADD_C : begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = IMMD_VAL; end 
            OC8051_RL    : begin aluctl = SHF_RL_OPR; first_opr = ACC_MEM;   second_opr = NONE_VAL; end
            OC8051_RET   : begin aluctl = MOV_OPR;    first_opr = NON_MEM;   second_opr = INT_VAL;  end

            OC8051_ADDC_R: begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = REG_GROUP;end 
            OC8051_ADDC_I: begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end 
            OC8051_ADDC_D: begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end 
            OC8051_ADDC_C: begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = IMMD_VAL; end 
            OC8051_RLC   : begin aluctl = SHF_RL_OPR; first_opr = ACC_MEM;   second_opr = NONE_VAL; end
            OC8051_RET1  : begin aluctl = MOV_OPR;    first_opr = NON_MEM;   second_opr = INT_VAL;  end
            OC8051_JNB   : begin aluctl = ADD_OPR;    first_opr = PC_MEM;    second_opr = INT_VAL;  end

            OC8051_ORL_R : begin aluctl = ORL_OPR;    first_opr = ACC_MEM;   second_opr = REG_GROUP;end
            OC8051_ORL_I : begin aluctl = ORL_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end
            OC8051_ORL_D : begin aluctl = ORL_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end
            OC8051_ORL_C : begin aluctl = ORL_OPR;    first_opr = ACC_MEM;   second_opr = IMMD_VAL; end
            OC8051_ORL_AD: begin aluctl = ORL_OPR;    first_opr = INT_MEM;   second_opr = ACC_MEM;  end
            OC8051_ORL_CD: begin aluctl = ORL_OPR;    first_opr = INT_MEM;   second_opr = IMMD_VAL; end
            OC8051_JC    : begin aluctl = ADD_OPR;    first_opr = PC_MEM;    second_opr = INT_VAL;  end

            OC8051_ANL_R : begin aluctl = ANL_OPR;    first_opr = ACC_MEM;   second_opr = REG_GROUP;end
            OC8051_ANL_I : begin aluctl = ANL_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end
            OC8051_ANL_D : begin aluctl = ANL_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end
            OC8051_ANL_C : begin aluctl = ANL_OPR;    first_opr = ACC_MEM;   second_opr = IMMD_VAL; end
            OC8051_ANL_AD: begin aluctl = ANL_OPR;    first_opr = INT_MEM;   second_opr = ACC_MEM;  end
            OC8051_ANL_CD: begin aluctl = ANL_OPR;    first_opr = INT_MEM;   second_opr = IMMD_VAL; end
            OC8051_JNC   : begin aluctl = ADD_OPR;    first_opr = PC_MEM;    second_opr = INT_VAL;  end

            OC8051_XRL_R : begin aluctl = XRL_OPR;    first_opr = ACC_MEM;   second_opr = REG_GROUP;end
            OC8051_XRL_I : begin aluctl = XRL_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end
            OC8051_XRL_D : begin aluctl = XRL_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end
            OC8051_XRL_C : begin aluctl = XRL_OPR;    first_opr = ACC_MEM;   second_opr = IMMD_VAL; end
            OC8051_XRL_AD: begin aluctl = XRL_OPR;    first_opr = INT_MEM;   second_opr = ACC_MEM;  end
            OC8051_XRL_CD: begin aluctl = XRL_OPR;    first_opr = INT_MEM;   second_opr = IMMD_VAL; end
            OC8051_JZ    : begin aluctl = ADD_OPR;    first_opr = PC_MEM;    second_opr = INT_VAL;  end

            OC8051_MOV_CR: begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOV_CI: begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOV_C : begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOV_CD: begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_JMP_D : begin aluctl = ADD_OPR;    first_opr = PC_MEM;    second_opr = INT_VAL;  end
            OC8051_JNZ   : begin aluctl = ADD_OPR;    first_opr = PC_MEM;    second_opr = INT_VAL;  end

            OC8051_MOV_RD: begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOV_ID: begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOVC_PC:begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOV_DD: begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_DIV   : begin aluctl = DIV_OPR;    first_opr = ACC_MEM;   second_opr = INT_VAL;  end
            OC8051_SJMP  : begin aluctl = ADD_OPR;    first_opr = PC_MEM;    second_opr = IMMD_VAL; end

            OC8051_SUBB_R: begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = REG_GROUP;end
            OC8051_SUBB_I: begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end
            OC8051_SUBB_D: begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end
            OC8051_SUBB_C: begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = IMMD_VAL; end
            OC8051_MOV_CB: begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOV_DP: begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOVC_DP:begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end

            OC8051_MOV_DR: begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOV_DI: begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOV_BC: begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MUL   : begin aluctl = MUL_OPR;    first_opr = ACC_VAL;   second_opr = BCC_VAL;  end
            OC8051_INC_DP: begin aluctl = ADD_OPR;    first_opr = DPTR;      second_opr = IMMD_VAL; end

            OC8051_CJNE_R: begin aluctl = ADD_OPR;    first_opr = REG_GRP;   second_opr = IMMD_VAL; end
            OC8051_CJNE_I: begin aluctl = ADD_OPR;    first_opr = INT_MEM;   second_opr = IMMD_VAL; end
            OC8051_CJNE_D: begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM ; end
            OC8051_CJNE_C: begin aluctl = ADD_OPR;    first_opr = ACC_MEM;   second_opr = IMMD_VAL; end

            OC8051_XCH_R : begin aluctl = XCH_OPR;    first_opr = ACC_MEM;   second_opr = REG_GRP;  end
            OC8051_XCH_I : begin aluctl = XCH_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end
            OC8051_XCH_D : begin aluctl = XCH_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end
            OC8051_PUSH  : begin aluctl = PUSH_OPR;   first_opr = ACC_MEM;   second_opr = NON_MEM;  end
            OC8051_SWAP  : begin aluctl = SWAP_OPR;   first_opr = ACC_MEM;   second_opr = NON_MEM;  end

            OC8051_DJNZ_R: begin aluctl = ADD_OPR;    first_opr = REG_GRP;   second_opr = IMMD_VAL; end
            OC8051_XCHD  : begin aluctl = XCHD_OPR;   first_opr = ACC_MEM;   second_opr = REG_GRP;  end
            OC8051_DJNZ_D: begin aluctl = XCH_OPR;    first_opr = ACC_MEM;   second_opr = INT_MEM;  end
            OC8051_POP   : begin aluctl = PUSH_OPR;   first_opr = ACC_MEM;   second_opr = NON_MEM;  end 
            OC8051_DA    : begin aluctl = DA_OPR;     first_opr = ACC_MEM;   second_opr = NON_MEM;  end

            OC8051_MOV_R : begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOV_I : begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOVX_IA:begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOV_D : begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOVX_PA:begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_CLR_A : begin aluctl = CLR_OPR;    first_opr = NON_VAL;   second_opr = ACC_VAL;  end

            OC8051_MOV_AR: begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOV_AI: begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOVX_AI:begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOV_DA: begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_MOVX_AP:begin aluctl = MOV_OPR;    first_opr = NON_VAL;   second_opr = IMMD_VAL; end
            OC8051_CPL_A : begin aluctl = CLR_OPR;    first_opr = NON_VAL;   second_opr = ACC_VAL;  end

            OC8051_AJMP  : begin aluctl = CLR_OPR;    first_opr = NON_VAL;   second_opr = ACC_VAL;  end
            OC8051_ACALL : begin aluctl = CLR_OPR;    first_opr = NON_VAL;   second_opr = ACC_VAL;  end

            default      : begin aluctl = NON_OPR;    first_opr = NON_VAL;   second_opr = NON_VAL;  end
        endcase 
    end

    always @(posedge clock or posedge reset)
    begin
        if (reset) begin
            inst_reg <= 0;
        end else if (state_8051 == FETCH) begin
            if      (inst_num_cnt == 0) inst_reg[23:16] <= fsm8051_inst_in;
            else if (inst_num_cnt == 1) inst_reg[15:8]  <= fsm8051_inst_in;
            else if (inst_num_cnt == 2) inst_reg[7:0]   <= fsm8051_inst_in;
        end
    end
    assign fsm8051_inst_out = inst_reg;

endmodule