xsimtest__v.cpp

自己定制自己的cpu

#include "isim/work/test__v/test__v.h"
#include "isim/work/glbl/glbl.h"
static const char * HSimCopyRightNotice = "Copyright 2004-2005, Xilinx Inc. All rights reserved.";


#include "work/test__v/test__v.h"
static HSim__s6* IF0(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMtest__v(label); 
    return blk;
}


#include "work/pc/pc.h"
static HSim__s6* IF1(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMpc(label); 
    return blk;
}


#include "work/ir/ir.h"
static HSim__s6* IF2(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMir(label); 
    return blk;
}


#include "work/dr/dr.h"
static HSim__s6* IF3(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMdr(label); 
    return blk;
}


#include "work/control/control.h"
static HSim__s6* IF4(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMcontrol(label); 
    return blk;
}


#include "work/ar/ar.h"
static HSim__s6* IF5(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMar(label); 
    return blk;
}


#include "work/alu/alu.h"
static HSim__s6* IF6(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMalu(label); 
    return blk;
}


#include "work/ac/ac.h"
static HSim__s6* IF7(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMac(label); 
    return blk;
}


#include "work/mem/mem.h"
static HSim__s6* IF8(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMmem(label); 
    return blk;
}


#include "work/cpu/cpu.h"
static HSim__s6* IF9(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMcpu(label); 
    return blk;
}


#include "work/glbl/glbl.h"
static HSim__s6* IF10(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMglbl(label); 
    return blk;
}

class _top : public HSim__s6 {
public:
    _top() : HSim__s6(false, "_top", "_top", 0, 0, HSim::VerilogModule) {}
    HSimConfigDecl * topModuleInstantiate() {
        HSimConfigDecl * cfgvh = 0;
        cfgvh = new HSimConfigDecl("default");
        (*cfgvh).addVlogModule("test_v", (HSimInstFactoryPtr)IF0);
        (*cfgvh).addVlogModule("pc", (HSimInstFactoryPtr)IF1);
        (*cfgvh).addVlogModule("ir", (HSimInstFactoryPtr)IF2);
        (*cfgvh).addVlogModule("dr", (HSimInstFactoryPtr)IF3);
        (*cfgvh).addVlogModule("control", (HSimInstFactoryPtr)IF4);
        (*cfgvh).addVlogModule("ar", (HSimInstFactoryPtr)IF5);
        (*cfgvh).addVlogModule("alu", (HSimInstFactoryPtr)IF6);
        (*cfgvh).addVlogModule("ac", (HSimInstFactoryPtr)IF7);
        (*cfgvh).addVlogModule("mem", (HSimInstFactoryPtr)IF8);
        (*cfgvh).addVlogModule("cpu", (HSimInstFactoryPtr)IF9);
        (*cfgvh).addVlogModule("glbl", (HSimInstFactoryPtr)IF10);
        HSim__s5 * topvl = 0;
        topvl = new workMtest__v("test_v");
        topvl->moduleInstantiate(cfgvh);
        addChild(topvl);
        topvl = new workMglbl("glbl");
        topvl->moduleInstantiate(cfgvh);
        addChild(topvl);
        return cfgvh;
}
};

main(int argc, char **argv) {
  HSimDesign::initDesign();
  globalKernel->getOptions(argc,argv);
  HSim__s6 * _top_i = 0;
  try {
    HSimConfigDecl *cfg;
 _top_i = new _top();
  cfg =  _top_i->topModuleInstantiate();
    return globalKernel->runTcl(cfg, _top_i, "_top", argc, argv);
  }
  catch (HSimError& msg){
    try {
      globalKernel->error(msg.ErrMsg);
      return 1;
    }
    catch(...) {}
      return 1;
  }
  catch (...){
    globalKernel->fatalError();
    return 1;
  }
}