📄 lcd1602_b.v
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//////////////////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.2.52 Mar. 28, 2005
// Thu Sep 6 12:56:06 2007
//
// Input file : E:/fpga_work/lcd/LCD1602.vhd
// Design name : LCD1602
// Author :
// Company :
//
// Description :
//
//
//////////////////////////////////////////////////////////////////////////////////////////////
//
//--------------------------------------------------------------------------------
// Company:
// Engineer:
//
// Create Date: 16:23:10 08/29/2007
// Design Name:
// Module Name: LCD1602 - Behavioral
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//--------------------------------------------------------------------------------
//-- Uncomment the following library declaration if instantiating
//-- any Xilinx primitives in this code.
//library UNISIM;
//use UNISIM.VComponents.all;
module LCD1602 (CLK, Reset, LCD_RS, LCD_RW, LCD_EN, data);
input CLK;
input Reset;
output LCD_RS;
reg LCD_RS;
output LCD_RW;
wire LCD_RW;
output LCD_EN;
wire LCD_EN;
output[3:0] data;
reg[3:0] data;
parameter[2:0] Write_instr = 0;
parameter[2:0] Write_DataUP4_1 = 1;
parameter[2:0] Write_DataDown4_1 = 2;
parameter[2:0] Set_DDRamAddUp = 3;
parameter[2:0] Set_DDRamAddDown = 4;
parameter[2:0] Write_DataUP4_2 = 5;
parameter[2:0] Write_DataDown4_2 = 6;
reg[2:0] State;
wire[7:0] MyRamUp[0:15];
wire[7:0] MyRamDown[0:15];
reg LCD_Clk;
reg[3:0] datacnt;
initial
begin
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[0] <= x"46" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[1] <= x"68" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[2] <= x"69" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[3] <= x"73" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[4] <= x"20" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[5] <= x"49" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[6] <= x"73" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[7] <= x"20" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[8] <= x"4d" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[9] <= x"79" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[10] <= x"20" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[11] <= x"46" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[12] <= x"69" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[13] <= x"72" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[14] <= x"73" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamUp[15] <= x"74" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[0] <= x"20" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[1] <= x"20" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[2] <= x"46" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[3] <= x"50" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[4] <= x"47" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[5] <= x"41" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[6] <= x"20" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[7] <= x"50" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[8] <= x"72" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[9] <= x"6f" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[10] <= x"67" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[11] <= x"72" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[12] <= x"61" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[13] <= x"6d" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[14] <= x"20" /* <<X-HDL>> Non-translatable radix */ ;
//<<X-HDL>> Cannot initialize wire type
// MyRamDown[15] <= x"20" /* <<X-HDL>> Non-translatable radix */ ;
LCD_Clk <= 1'b0;
datacnt <= 0;
end
reg [7:0] MyRamUp_xhdl;
reg [7:0] MyRamDown_xhdl;
assign LCD_RW = 1'b0 ;
assign LCD_EN = LCD_Clk ;
always @(posedge CLK)
begin : xhdl_3
reg[14:0] n1;
if (n1 < 19999)
begin
n1 = n1 + 1;
end
else
begin
n1 = 0;
LCD_Clk <= ~LCD_Clk ;
end
end
always @(posedge LCD_Clk or negedge Reset)
begin
if (Reset == 1'b0)
begin
State <= Write_instr ;
LCD_RS <= 1'b0 ;
end
else
begin
case (State)
Write_instr :
begin
LCD_RS <= 1'b0 ;
if (datacnt == 0)
begin
data <= 4'b0011 ;
datacnt <= datacnt + 1 ;
end
else if (datacnt == 1)
begin
data <= 4'b0011 ;
datacnt <= datacnt + 1 ;
end
else if (datacnt == 2)
begin
data <= 4'b0011 ;
datacnt <= datacnt + 1 ;
end
else if (datacnt == 3)
begin
data <= 4'b0010 ;
datacnt <= datacnt + 1 ;
end
else if (datacnt == 4)
begin
data <= 4'b0010 ;
datacnt <= datacnt + 1 ;
end
else if (datacnt == 5)
begin
data <= 4'b1000 ;
datacnt <= datacnt + 1 ;
end
else if (datacnt == 6)
begin
data <= 4'b0000 ;
datacnt <= datacnt + 1 ;
end
else if (datacnt == 7)
begin
data <= 4'b0110 ;
datacnt <= datacnt + 1 ;
end
else if (datacnt == 8)
begin
data <= 4'b0000 ;
datacnt <= datacnt + 1 ;
end
else if (datacnt == 9)
begin
data <= 4'b1100 ;
datacnt <= datacnt + 1 ;
end
else if (datacnt == 10)
begin
data <= 4'b1000 ;
datacnt <= datacnt + 1 ;
end
else
begin
data <= 4'b0000 ;
datacnt <= 0 ;
State <= Write_DataUP4_1 ;
end
end
Write_DataUP4_1 :
begin
LCD_RS <= 1'b1 ;
MyRamUp_xhdl = MyRamUp[datacnt];
data <= MyRamUp_xhdl[7:4] ;
MyRamUp[datacnt] <= MyRamUp_xhdl;
State <= Write_DataDown4_1 ;
end
Write_DataDown4_1 :
begin
if (datacnt == 15)
begin
data <= MyRamUp_xhdl[3:0] ;
datacnt <= 0 ;
State <= Set_DDRamAddUp ;
end
else
begin
data <= MyRamUp_xhdl[3:0] ;
datacnt <= datacnt + 1 ;
State <= Write_DataUP4_1 ;
end
end
Set_DDRamAddUp :
begin
LCD_RS <= 1'b0 ;
data <= 4'b1100 ;
State <= Set_DDRamAddDown ;
end
Set_DDRamAddDown :
begin
data <= 4'b0000 ;
State <= Write_DataUP4_2 ;
end
Write_DataUP4_2 :
begin
LCD_RS <= 1'b1 ;
MyRamDown_xhdl = MyRamDown[datacnt];
data <= MyRamDown_xhdl[7:4] ;
MyRamDown[datacnt] <= MyRamDown_xhdl;
State <= Write_DataDown4_2 ;
end
Write_DataDown4_2 :
begin
if (datacnt == 15)
begin
data <= MyRamDown_xhdl[3:0] ;
datacnt <= 0 ;
State <= Write_DataUP4_1 ;
end
else
begin
data <= MyRamDown_xhdl[3:0] ;
datacnt <= datacnt + 1 ;
State <= Write_DataUP4_2 ;
end
end
default :
begin
State <= Write_instr ;
end
endcase
end
end
endmodule
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