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output35 & output36 & output37 & output38 & !output39 &
output310 & output311);
-- Node name is ':8' = 'output38'
-- Equation name is 'output38', location is LC027, type is buried.
output38 = DFFE( _EQ032 $ GND, GLOBAL( input_high), VCC, VCC, VCC);
_EQ032 = output30 & output31 & output32 & output33 & output34 &
output35 & output36 & output37 & !output38 & _X001
# output38 & _X001 & _X011;
_X001 = EXP( output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output310 & output311);
_X011 = EXP( output30 & output31 & output32 & output33 & output34 &
output35 & output36 & output37);
-- Node name is ':7' = 'output39'
-- Equation name is 'output39', location is LC048, type is buried.
output39 = DFFE( _EQ033 $ GND, GLOBAL( input_high), VCC, VCC, VCC);
_EQ033 = output30 & output31 & output32 & output33 & output34 &
output35 & output36 & output37 & output38 & !output39 &
_X001
# !output38 & output39 & _X001
# output39 & _X001 & _X011;
_X001 = EXP( output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output310 & output311);
_X011 = EXP( output30 & output31 & output32 & output33 & output34 &
output35 & output36 & output37);
-- Node name is ':32' = 'output110'
-- Equation name is 'output110', location is LC062, type is buried.
output110 = DFFE( _EQ034 $ VCC, GLOBAL( input_high), VCC, VCC, VCC);
_EQ034 = !_LC030 & output10 & output11 & output12 & output13 &
output14 & !output15 & !output16 & output17 & output18 &
output19 & output110 & output111 & _X002
# output20 & output21 & output22 & !output23 & output24 &
output25 & !output26 & output27 & !output28 & output29 &
!output110 & output210 & output211
# !_LC030 & _LC060 & output18 & output19 & output110 & _X002
# !output110 & _X012;
_X002 = EXP( output20 & output21 & output22 & !output23 & output24 &
output25 & !output26 & output27 & !output28 & output29 &
output210 & output211);
_X012 = EXP(!_LC030 & output10 & output11 & output12 & output13 &
output14 & output15 & output16 & output17 & output18 &
output19);
-- Node name is ':31' = 'output111'
-- Equation name is 'output111', location is LC025, type is buried.
output111 = DFFE( _EQ035 $ GND, GLOBAL( input_high), VCC, VCC, VCC);
_EQ035 = output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output111 & output310 & output311
# _LC057 & _X001;
_X001 = EXP( output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output310 & output311);
-- Node name is ':19' = 'output210'
-- Equation name is 'output210', location is LC045, type is buried.
output210 = TFFE( _EQ036, GLOBAL( input_high), VCC, VCC, VCC);
_EQ036 = !_LC030 & output20 & output21 & output22 & !output23 &
output24 & output25 & !output26 & output27 & !output28 &
output29 & output210 & output211
# _LC053 & output28 & output29 & _X001;
_X001 = EXP( output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output310 & output311);
-- Node name is ':18' = 'output211'
-- Equation name is 'output211', location is LC046, type is buried.
output211 = TFFE( _EQ037, GLOBAL( input_high), VCC, VCC, VCC);
_EQ037 = !_LC030 & output20 & output21 & output22 & !output23 &
output24 & output25 & !output26 & output27 & !output28 &
output29 & output210 & output211
# _LC053 & output28 & output29 & output210 & _X001;
_X001 = EXP( output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output310 & output311);
-- Node name is ':6' = 'output310'
-- Equation name is 'output310', location is LC033, type is buried.
output310 = TFFE( _EQ038, GLOBAL( input_high), VCC, VCC, VCC);
_EQ038 = output30 & output31 & output32 & output33 & output34 &
output35 & output36 & output37 & output38 & output39 &
!output310 & _X001
# output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output310 & output311
# output30 & output31 & output32 & output33 & output34 &
output35 & output36 & output37 & output38 & output39 &
output310;
_X001 = EXP( output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output310 & output311);
-- Node name is ':5' = 'output311'
-- Equation name is 'output311', location is LC047, type is buried.
output311 = TFFE( _EQ039, GLOBAL( input_high), VCC, VCC, VCC);
_EQ039 = output30 & output31 & output32 & output33 & output34 &
output35 & output36 & output37 & output38 & output39 &
output310 & !output311 & _X001
# output30 & output31 & output32 & output33 & output34 &
output35 & output36 & output37 & output38 & output39 &
output310 & output311
# output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output310 & output311;
_X001 = EXP( output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output310 & output311);
-- Node name is '|LPM_ADD_SUB:380|addcore:adder|addcore:adder0|cout_node' from file "addcore.tdf" line 165, column 5
-- Equation name is '_LC053', type is buried
_LC053 = LCELL( _EQ040 $ GND);
_EQ040 = output20 & output21 & output22 & output23 & output24 &
output25 & output26 & output27;
-- Node name is '|LPM_ADD_SUB:505|addcore:adder|addcore:adder0|cout_node' from file "addcore.tdf" line 165, column 5
-- Equation name is '_LC060', type is buried
_LC060 = LCELL( _EQ041 $ GND);
_EQ041 = output10 & output11 & output12 & output13 & output14 &
output15 & output16 & output17;
-- Node name is '|LPM_ADD_SUB:505|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC054', type is buried
_LC054 = LCELL( _EQ042 $ GND);
_EQ042 = output10 & output11 & output12 & output13;
-- Node name is '~654~1'
-- Equation name is '~654~1', location is LC059, type is buried.
-- synthesized logic cell
_LC059 = LCELL( _EQ043 $ output_low1);
_EQ043 = !output_low1 & output10 & output11 & output12 & output13 &
output14 & !output15 & !output16 & output17 & output18 &
output19 & output110 & output111;
-- Node name is '~855~1'
-- Equation name is '~855~1', location is LC058, type is buried.
-- synthesized logic cell
_LC058 = LCELL( _EQ044 $ GND);
_EQ044 = output_low1 & output20 & output21 & output22 & !output23 &
output24 & output25 & !output26 & output27 & !output28 &
output29 & output210 & output211
# _LC059 & _X002;
_X002 = EXP( output20 & output21 & output22 & !output23 & output24 &
output25 & !output26 & output27 & !output28 & output29 &
output210 & output211);
-- Node name is '~857~1'
-- Equation name is '~857~1', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ045 $ GND);
_EQ045 = output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output310 & output311;
-- Node name is '~864~1'
-- Equation name is '~864~1', location is LC057, type is buried.
-- synthesized logic cell
_LC057 = LCELL( _EQ046 $ VCC);
_EQ046 = output10 & output11 & output12 & output13 & output14 &
!output15 & !output16 & output17 & output18 & output19 &
output110 & _X002 & _X013
# output20 & output21 & output22 & !output23 & output24 &
output25 & !output26 & output27 & !output28 & output29 &
!output111 & output210 & output211
# _LC054 & output14 & output15 & output16 & output17 &
output18 & output19 & output110 & output111 & _X002
# !output111 & _X014;
_X002 = EXP( output20 & output21 & output22 & !output23 & output24 &
output25 & !output26 & output27 & !output28 & output29 &
output210 & output211);
_X013 = EXP( output10 & output11 & output12 & output13 & output14 &
output15 & output16 & output17);
_X014 = EXP( output10 & output11 & output12 & output13 & output14 &
output15 & output16 & output17 & output18 & output19 &
output110);
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs B, C
-- _X011 occurs in LABs B, C
Project Information e:\dividefre\dividefre.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,490K
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