📄 dividefre.rpt
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- 55 D TFFE + t 1 1 0 0 19 0 8 output16 (:36)
(36) 52 D DFFE + t 2 1 0 0 25 0 9 output15 (:37)
- 61 D TFFE + t 1 1 0 0 17 0 9 output14 (:38)
- 39 C TFFE + t 1 0 1 0 27 0 11 output13 (:39)
(29) 41 C TFFE + t 0 0 0 0 26 0 12 output12 (:40)
- 42 C TFFE + t 0 0 0 0 25 0 13 output11 (:41)
- 43 C TFFE + t 0 0 0 0 24 0 14 output10 (:42)
- 59 D SOFT s t 0 0 0 0 13 0 1 ~654~1
- 58 D SOFT s t 1 1 0 0 14 1 0 ~855~1
(14) 30 B SOFT s t 0 0 0 0 12 1 14 ~857~1
(39) 57 D SOFT s t 3 1 0 0 25 0 1 ~864~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\dividefre\dividefre.rpt
dividefre
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------------------- LC17 output_low1
| +------------------------- LC19 output_low3
| | +----------------------- LC27 output38
| | | +--------------------- LC31 output37
| | | | +------------------- LC18 output36
| | | | | +----------------- LC21 output35
| | | | | | +--------------- LC22 output34
| | | | | | | +------------- LC29 output33
| | | | | | | | +----------- LC28 output32
| | | | | | | | | +--------- LC24 output31
| | | | | | | | | | +------- LC23 output30
| | | | | | | | | | | +----- LC20 output20
| | | | | | | | | | | | +--- LC25 output111
| | | | | | | | | | | | | +- LC30 ~857~1
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC17 -> * - - - - - - - - - - - - - | - * - * | <-- output_low1
LC19 -> - * - - - - - - - - - - - - | - * - - | <-- output_low3
LC27 -> * * * * * * * * * * * * * * | - * * - | <-- output38
LC31 -> * * * * * * * * * * * * * * | - * * - | <-- output37
LC18 -> * * * * * * * * * * * * * * | - * * - | <-- output36
LC21 -> * * * * * * * * * * * * * * | - * * - | <-- output35
LC22 -> * * * * * * * * * * * * * * | - * * - | <-- output34
LC29 -> * * * * * * * * * * * * * * | - * * - | <-- output33
LC28 -> * * * * * * * * * * * * * * | - * * - | <-- output32
LC24 -> * * * * * * * * * * * * * * | - * * - | <-- output31
LC23 -> * * * * * * * * * * * * * * | - * * - | <-- output30
LC25 -> - - - - - - - - - - - - * - | - * - * | <-- output111
Pin
43 -> - - - - - - - - - - - - - - | - - - - | <-- input_high
LC47 -> * * * * * * * * * * * * * * | - * * - | <-- output311
LC33 -> * * * * * * * * * * * * * * | - * * - | <-- output310
LC48 -> * * * * * * * * * * * * * * | - * * - | <-- output39
LC58 -> * - - - - - - - - - - - - - | - * - - | <-- ~855~1
LC57 -> - - - - - - - - - - - - * - | - * - - | <-- ~864~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\dividefre\dividefre.rpt
dividefre
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC47 output311
| +----------------------------- LC33 output310
| | +--------------------------- LC48 output39
| | | +------------------------- LC46 output211
| | | | +----------------------- LC45 output210
| | | | | +--------------------- LC44 output29
| | | | | | +------------------- LC34 output28
| | | | | | | +----------------- LC35 output25
| | | | | | | | +--------------- LC36 output24
| | | | | | | | | +------------- LC37 output23
| | | | | | | | | | +----------- LC38 output22
| | | | | | | | | | | +--------- LC40 output21
| | | | | | | | | | | | +------- LC39 output13
| | | | | | | | | | | | | +----- LC41 output12
| | | | | | | | | | | | | | +--- LC42 output11
| | | | | | | | | | | | | | | +- LC43 output10
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC47 -> * * * * * * * * * * * * * * * * | - * * - | <-- output311
LC33 -> * * * * * * * * * * * * * * * * | - * * - | <-- output310
LC48 -> * * * * * * * * * * * * * * * * | - * * - | <-- output39
LC46 -> - - - * * * * * * * - - * * * * | - - * * | <-- output211
LC45 -> - - - * * * * * * * - - * * * * | - - * * | <-- output210
LC44 -> - - - * * * * * * * - - * * * * | - - * * | <-- output29
LC34 -> - - - * * * * * * * - - * * * * | - - * * | <-- output28
LC35 -> - - - * * * * * * * - - * * * * | - - * * | <-- output25
LC36 -> - - - * * * * * * * - - * * * * | - - * * | <-- output24
LC37 -> - - - * * * * * * * - - * * * * | - - * * | <-- output23
LC38 -> - - - * * * * * * * * - * * * * | - - * * | <-- output22
LC40 -> - - - * * * * * * * * * * * * * | - - * * | <-- output21
LC41 -> - - - - - - - - - - - - * * - - | - - * * | <-- output12
LC42 -> - - - - - - - - - - - - * * * - | - - * * | <-- output11
LC43 -> - - - - - - - - - - - - * * * * | - - * * | <-- output10
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- input_high
LC53 -> - - - * * * - - - - - - - - - - | - - * - | <-- |LPM_ADD_SUB:380|addcore:adder|addcore:adder0|cout_node
LC27 -> * * * * * * * * * * * * * * * * | - * * - | <-- output38
LC31 -> * * * * * * * * * * * * * * * * | - * * - | <-- output37
LC18 -> * * * * * * * * * * * * * * * * | - * * - | <-- output36
LC21 -> * * * * * * * * * * * * * * * * | - * * - | <-- output35
LC22 -> * * * * * * * * * * * * * * * * | - * * - | <-- output34
LC29 -> * * * * * * * * * * * * * * * * | - * * - | <-- output33
LC28 -> * * * * * * * * * * * * * * * * | - * * - | <-- output32
LC24 -> * * * * * * * * * * * * * * * * | - * * - | <-- output31
LC23 -> * * * * * * * * * * * * * * * * | - * * - | <-- output30
LC50 -> - - - * * * * * * * - - * * * * | - - * * | <-- output27
LC51 -> - - - * * * * * * * - - * * * * | - - * * | <-- output26
LC20 -> - - - * * * * * * * * * * * * * | - - * * | <-- output20
LC30 -> - - - * * * - * * - - - - - - - | - - * * | <-- ~857~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\dividefre\dividefre.rpt
dividefre
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC53 |LPM_ADD_SUB:380|addcore:adder|addcore:adder0|cout_node
| +----------------------------- LC60 |LPM_ADD_SUB:505|addcore:adder|addcore:adder0|cout_node
| | +--------------------------- LC54 |LPM_ADD_SUB:505|addcore:adder|addcore:adder0|g4
| | | +------------------------- LC49 output_low2
| | | | +----------------------- LC50 output27
| | | | | +--------------------- LC51 output26
| | | | | | +------------------- LC62 output110
| | | | | | | +----------------- LC56 output19
| | | | | | | | +--------------- LC63 output18
| | | | | | | | | +------------- LC64 output17
| | | | | | | | | | +----------- LC55 output16
| | | | | | | | | | | +--------- LC52 output15
| | | | | | | | | | | | +------- LC61 output14
| | | | | | | | | | | | | +----- LC59 ~654~1
| | | | | | | | | | | | | | +--- LC58 ~855~1
| | | | | | | | | | | | | | | +- LC57 ~864~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC60 -> - - - - - - * * * - - - - - - - | - - - * | <-- |LPM_ADD_SUB:505|addcore:adder|addcore:adder0|cout_node
LC54 -> - - - - - - - - - - - - - - - * | - - - * | <-- |LPM_ADD_SUB:505|addcore:adder|addcore:adder0|g4
LC49 -> - - - * - - - - - - - - - - - - | - - - * | <-- output_low2
LC50 -> * - - * * - * * * * * * * - * * | - - * * | <-- output27
LC51 -> * - - * * * * * * * * * * - * * | - - * * | <-- output26
LC62 -> - - - - - - * * * * - * - * - * | - - - * | <-- output110
LC56 -> - - - - - - * * * * - * - * - * | - - - * | <-- output19
LC63 -> - - - - - - * * * * - * - * - * | - - - * | <-- output18
LC64 -> - * - - - - * * * * - * - * - * | - - - * | <-- output17
LC55 -> - * - - - - * * * * * * - * - * | - - - * | <-- output16
LC52 -> - * - - - - * * * * * * - * - * | - - - * | <-- output15
LC61 -> - * - - - - * * * * * * * * - * | - - - * | <-- output14
LC59 -> - - - - - - - - - - - - - - * - | - - - * | <-- ~654~1
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- input_high
LC17 -> - - - - - - - - - - - - - * * - | - * - * | <-- output_low1
LC46 -> - - - * * - * * * * * * * - * * | - - * * | <-- output211
LC45 -> - - - * * - * * * * * * * - * * | - - * * | <-- output210
LC44 -> - - - * * - * * * * * * * - * * | - - * * | <-- output29
LC34 -> - - - * * - * * * * * * * - * * | - - * * | <-- output28
LC35 -> * - - * * * * * * * * * * - * * | - - * * | <-- output25
LC36 -> * - - * * * * * * * * * * - * * | - - * * | <-- output24
LC37 -> * - - * * * * * * * * * * - * * | - - * * | <-- output23
LC38 -> * - - * * * * * * * * * * - * * | - - * * | <-- output22
LC40 -> * - - * * * * * * * * * * - * * | - - * * | <-- output21
LC20 -> * - - * * * * * * * * * * - * * | - - * * | <-- output20
LC25 -> - - - - - - * * * * - * - * - * | - * - * | <-- output111
LC39 -> - * * - - - * * * * * * * * - * | - - - * | <-- output13
LC41 -> - * * - - - * * * * * * * * - * | - - * * | <-- output12
LC42 -> - * * - - - * * * * * * * * - * | - - * * | <-- output11
LC43 -> - * * - - - * * * * * * * * - * | - - * * | <-- output10
LC30 -> - - - * * * * * * * * * * - - - | - - * * | <-- ~857~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\dividefre\dividefre.rpt
dividefre
** EQUATIONS **
input_high : INPUT;
-- Node name is 'output_low1' = 'output_1'
-- Equation name is 'output_low1', location is LC017, type is output.
output_low1 = DFFE( _EQ001 $ GND, GLOBAL( input_high), VCC, VCC, VCC);
_EQ001 = output_low1 & output30 & output31 & !output32 & !output33 &
!output34 & output35 & output36 & output37 & output38 &
!output39 & output310 & output311
# _LC058 & _X001;
_X001 = EXP( output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output310 & output311);
-- Node name is 'output_low2' = 'output_2'
-- Equation name is 'output_low2', location is LC049, type is output.
output_low2 = TFFE( _EQ002, GLOBAL( input_high), VCC, VCC, VCC);
_EQ002 = !_LC030 & !output_low2 & output20 & output21 & output22 &
!output23 & output24 & output25 & !output26 & output27 &
!output28 & output29 & output210 & output211;
-- Node name is 'output_low3' = 'output_3'
-- Equation name is 'output_low3', location is LC019, type is output.
output_low3 = TFFE( _EQ003, GLOBAL( input_high), VCC, VCC, VCC);
_EQ003 = !output_low3 & output30 & output31 & !output32 & !output33 &
!output34 & output35 & output36 & output37 & output38 &
!output39 & output310 & output311;
-- Node name is ':42' = 'output10'
-- Equation name is 'output10', location is LC043, type is buried.
output10 = TFFE(!_EQ004, GLOBAL( input_high), VCC, VCC, VCC);
_EQ004 = output20 & output21 & output22 & !output23 & output24 &
output25 & !output26 & output27 & !output28 & output29 &
output210 & output211
# output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output310 & output311;
-- Node name is ':41' = 'output11'
-- Equation name is 'output11', location is LC042, type is buried.
output11 = TFFE(!_EQ005, GLOBAL( input_high), VCC, VCC, VCC);
_EQ005 = output20 & output21 & output22 & !output23 & output24 &
output25 & !output26 & output27 & !output28 & output29 &
output210 & output211
# output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output310 & output311
# !output10;
-- Node name is ':40' = 'output12'
-- Equation name is 'output12', location is LC041, type is buried.
output12 = TFFE(!_EQ006, GLOBAL( input_high), VCC, VCC, VCC);
_EQ006 = output20 & output21 & output22 & !output23 & output24 &
output25 & !output26 & output27 & !output28 & output29 &
output210 & output211
# output30 & output31 & !output32 & !output33 & !output34 &
output35 & output36 & output37 & output38 & !output39 &
output310 & output311
# !output10
# !output11;
-- Node name is ':39' = 'output13'
-- Equation name is 'output13', location is LC039, type is buried.
output13 = TFFE(!_EQ007, GLOBAL( input_high), VCC, VCC, VCC);
_EQ007 = output20 & output21 & output22 & !output23 & output24 &
output25 & !output26 & output27 & !output28 & output29 &
output210 & output211
# output30 & output31 & !output32 & !output33 & !output34 &
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