uart.tan.qmsg

来自「自己用VHDL写的一个串口程序」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Info" "ITDB_TH_RESULT" "BEGINS:U0\|PRESENT_STATE.state3 START CLK -0.082 ns register " "Info: th for register \"BEGINS:U0\|PRESENT_STATE.state3\" (data pin = \"START\", clock pin = \"CLK\") is -0.082 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 8.136 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 8.136 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 12; CLK Node = 'CLK'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "UART.vhd" "" { Text "E:/mywork/UART/UART.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fenpin:U3\|CLK_REG3 2 REG LC_X14_Y10_N2 28 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X14_Y10_N2; Fanout = 28; REG Node = 'fenpin:U3\|CLK_REG3'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { CLK fenpin:U3|CLK_REG3 } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/mywork/UART/fenpin.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.276 ns) + CELL(0.711 ns) 8.136 ns BEGINS:U0\|PRESENT_STATE.state3 3 REG LC_X15_Y19_N6 7 " "Info: 3: + IC(4.276 ns) + CELL(0.711 ns) = 8.136 ns; Loc. = LC_X15_Y19_N6; Fanout = 7; REG Node = 'BEGINS:U0\|PRESENT_STATE.state3'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.987 ns" { fenpin:U3|CLK_REG3 BEGINS:U0|PRESENT_STATE.state3 } "NODE_NAME" } } { "BEGINS.vhd" "" { Text "E:/mywork/UART/BEGINS.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.29 % ) " "Info: Total cell delay = 3.115 ns ( 38.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.021 ns ( 61.71 % ) " "Info: Total interconnect delay = 5.021 ns ( 61.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { CLK fenpin:U3|CLK_REG3 BEGINS:U0|PRESENT_STATE.state3 } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { CLK CLK~out0 fenpin:U3|CLK_REG3 BEGINS:U0|PRESENT_STATE.state3 } { 0.000ns 0.000ns 0.745ns 4.276ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "BEGINS.vhd" "" { Text "E:/mywork/UART/BEGINS.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.233 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.233 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns START 1 PIN PIN_1 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 7; PIN Node = 'START'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { START } "NODE_NAME" } } { "UART.vhd" "" { Text "E:/mywork/UART/UART.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.455 ns) + CELL(0.309 ns) 8.233 ns BEGINS:U0\|PRESENT_STATE.state3 2 REG LC_X15_Y19_N6 7 " "Info: 2: + IC(6.455 ns) + CELL(0.309 ns) = 8.233 ns; Loc. = LC_X15_Y19_N6; Fanout = 7; REG Node = 'BEGINS:U0\|PRESENT_STATE.state3'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.764 ns" { START BEGINS:U0|PRESENT_STATE.state3 } "NODE_NAME" } } { "BEGINS.vhd" "" { Text "E:/mywork/UART/BEGINS.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 21.60 % ) " "Info: Total cell delay = 1.778 ns ( 21.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.455 ns ( 78.40 % ) " "Info: Total interconnect delay = 6.455 ns ( 78.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.233 ns" { START BEGINS:U0|PRESENT_STATE.state3 } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.233 ns" { START START~out0 BEGINS:U0|PRESENT_STATE.state3 } { 0.000ns 0.000ns 6.455ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { CLK fenpin:U3|CLK_REG3 BEGINS:U0|PRESENT_STATE.state3 } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { CLK CLK~out0 fenpin:U3|CLK_REG3 BEGINS:U0|PRESENT_STATE.state3 } { 0.000ns 0.000ns 0.745ns 4.276ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.233 ns" { START BEGINS:U0|PRESENT_STATE.state3 } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.233 ns" { START START~out0 BEGINS:U0|PRESENT_STATE.state3 } { 0.000ns 0.000ns 6.455ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "100 " "Info: Allocated 100 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 14 10:52:47 2007 " "Info: Processing ended: Mon May 14 10:52:47 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}