uart.tan.qmsg

来自「自己用VHDL写的一个串口程序」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fenpin:U3\|CLK_REG3 " "Info: Detected ripple clock \"fenpin:U3\|CLK_REG3\" as buffer" {  } { { "fenpin.vhd" "" { Text "E:/mywork/UART/fenpin.vhd" 16 -1 0 } } { "d:/tools/quartus7.0/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/tools/quartus7.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpin:U3\|CLK_REG3" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register TRANSMIT:U1\|TEMP\[1\] register TRANSMIT:U1\|TXD 199.52 MHz 5.012 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 199.52 MHz between source register \"TRANSMIT:U1\|TEMP\[1\]\" and destination register \"TRANSMIT:U1\|TXD\" (period= 5.012 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.751 ns + Longest register register " "Info: + Longest register to register delay is 4.751 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TRANSMIT:U1\|TEMP\[1\] 1 REG LC_X15_Y18_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y18_N5; Fanout = 3; REG Node = 'TRANSMIT:U1\|TEMP\[1\]'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { TRANSMIT:U1|TEMP[1] } "NODE_NAME" } } { "TRANSMIT.vhd" "" { Text "E:/mywork/UART/TRANSMIT.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.276 ns) + CELL(0.590 ns) 1.866 ns TRANSMIT:U1\|Equal0~32 2 COMB LC_X15_Y17_N6 16 " "Info: 2: + IC(1.276 ns) + CELL(0.590 ns) = 1.866 ns; Loc. = LC_X15_Y17_N6; Fanout = 16; COMB Node = 'TRANSMIT:U1\|Equal0~32'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.866 ns" { TRANSMIT:U1|TEMP[1] TRANSMIT:U1|Equal0~32 } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/tools/quartus7.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.695 ns) + CELL(0.442 ns) 3.003 ns TRANSMIT:U1\|Selector17~482 3 COMB LC_X15_Y17_N7 1 " "Info: 3: + IC(0.695 ns) + CELL(0.442 ns) = 3.003 ns; Loc. = LC_X15_Y17_N7; Fanout = 1; COMB Node = 'TRANSMIT:U1\|Selector17~482'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.137 ns" { TRANSMIT:U1|Equal0~32 TRANSMIT:U1|Selector17~482 } "NODE_NAME" } } { "TRANSMIT.vhd" "" { Text "E:/mywork/UART/TRANSMIT.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.439 ns) + CELL(0.292 ns) 3.734 ns TRANSMIT:U1\|Selector17~483 4 COMB LC_X15_Y17_N0 1 " "Info: 4: + IC(0.439 ns) + CELL(0.292 ns) = 3.734 ns; Loc. = LC_X15_Y17_N0; Fanout = 1; COMB Node = 'TRANSMIT:U1\|Selector17~483'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.731 ns" { TRANSMIT:U1|Selector17~482 TRANSMIT:U1|Selector17~483 } "NODE_NAME" } } { "TRANSMIT.vhd" "" { Text "E:/mywork/UART/TRANSMIT.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.410 ns) + CELL(0.607 ns) 4.751 ns TRANSMIT:U1\|TXD 5 REG LC_X15_Y17_N3 2 " "Info: 5: + IC(0.410 ns) + CELL(0.607 ns) = 4.751 ns; Loc. = LC_X15_Y17_N3; Fanout = 2; REG Node = 'TRANSMIT:U1\|TXD'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.017 ns" { TRANSMIT:U1|Selector17~483 TRANSMIT:U1|TXD } "NODE_NAME" } } { "TRANSMIT.vhd" "" { Text "E:/mywork/UART/TRANSMIT.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.931 ns ( 40.64 % ) " "Info: Total cell delay = 1.931 ns ( 40.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.820 ns ( 59.36 % ) " "Info: Total interconnect delay = 2.820 ns ( 59.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.751 ns" { TRANSMIT:U1|TEMP[1] TRANSMIT:U1|Equal0~32 TRANSMIT:U1|Selector17~482 TRANSMIT:U1|Selector17~483 TRANSMIT:U1|TXD } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "4.751 ns" { TRANSMIT:U1|TEMP[1] TRANSMIT:U1|Equal0~32 TRANSMIT:U1|Selector17~482 TRANSMIT:U1|Selector17~483 TRANSMIT:U1|TXD } { 0.000ns 1.276ns 0.695ns 0.439ns 0.410ns } { 0.000ns 0.590ns 0.442ns 0.292ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 8.136 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 8.136 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 12; CLK Node = 'CLK'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "UART.vhd" "" { Text "E:/mywork/UART/UART.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fenpin:U3\|CLK_REG3 2 REG LC_X14_Y10_N2 28 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X14_Y10_N2; Fanout = 28; REG Node = 'fenpin:U3\|CLK_REG3'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { CLK fenpin:U3|CLK_REG3 } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/mywork/UART/fenpin.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.276 ns) + CELL(0.711 ns) 8.136 ns TRANSMIT:U1\|TXD 3 REG LC_X15_Y17_N3 2 " "Info: 3: + IC(4.276 ns) + CELL(0.711 ns) = 8.136 ns; Loc. = LC_X15_Y17_N3; Fanout = 2; REG Node = 'TRANSMIT:U1\|TXD'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.987 ns" { fenpin:U3|CLK_REG3 TRANSMIT:U1|TXD } "NODE_NAME" } } { "TRANSMIT.vhd" "" { Text "E:/mywork/UART/TRANSMIT.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.29 % ) " "Info: Total cell delay = 3.115 ns ( 38.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.021 ns ( 61.71 % ) " "Info: Total interconnect delay = 5.021 ns ( 61.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { CLK fenpin:U3|CLK_REG3 TRANSMIT:U1|TXD } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { CLK CLK~out0 fenpin:U3|CLK_REG3 TRANSMIT:U1|TXD } { 0.000ns 0.000ns 0.745ns 4.276ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 8.136 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 8.136 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 12; CLK Node = 'CLK'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "UART.vhd" "" { Text "E:/mywork/UART/UART.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fenpin:U3\|CLK_REG3 2 REG LC_X14_Y10_N2 28 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X14_Y10_N2; Fanout = 28; REG Node = 'fenpin:U3\|CLK_REG3'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { CLK fenpin:U3|CLK_REG3 } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/mywork/UART/fenpin.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.276 ns) + CELL(0.711 ns) 8.136 ns TRANSMIT:U1\|TEMP\[1\] 3 REG LC_X15_Y18_N5 3 " "Info: 3: + IC(4.276 ns) + CELL(0.711 ns) = 8.136 ns; Loc. = LC_X15_Y18_N5; Fanout = 3; REG Node = 'TRANSMIT:U1\|TEMP\[1\]'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.987 ns" { fenpin:U3|CLK_REG3 TRANSMIT:U1|TEMP[1] } "NODE_NAME" } } { "TRANSMIT.vhd" "" { Text "E:/mywork/UART/TRANSMIT.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.29 % ) " "Info: Total cell delay = 3.115 ns ( 38.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.021 ns ( 61.71 % ) " "Info: Total interconnect delay = 5.021 ns ( 61.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { CLK fenpin:U3|CLK_REG3 TRANSMIT:U1|TEMP[1] } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { CLK CLK~out0 fenpin:U3|CLK_REG3 TRANSMIT:U1|TEMP[1] } { 0.000ns 0.000ns 0.745ns 4.276ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { CLK fenpin:U3|CLK_REG3 TRANSMIT:U1|TXD } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { CLK CLK~out0 fenpin:U3|CLK_REG3 TRANSMIT:U1|TXD } { 0.000ns 0.000ns 0.745ns 4.276ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { CLK fenpin:U3|CLK_REG3 TRANSMIT:U1|TEMP[1] } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { CLK CLK~out0 fenpin:U3|CLK_REG3 TRANSMIT:U1|TEMP[1] } { 0.000ns 0.000ns 0.745ns 4.276ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "TRANSMIT.vhd" "" { Text "E:/mywork/UART/TRANSMIT.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "TRANSMIT.vhd" "" { Text "E:/mywork/UART/TRANSMIT.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.751 ns" { TRANSMIT:U1|TEMP[1] TRANSMIT:U1|Equal0~32 TRANSMIT:U1|Selector17~482 TRANSMIT:U1|Selector17~483 TRANSMIT:U1|TXD } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "4.751 ns" { TRANSMIT:U1|TEMP[1] TRANSMIT:U1|Equal0~32 TRANSMIT:U1|Selector17~482 TRANSMIT:U1|Selector17~483 TRANSMIT:U1|TXD } { 0.000ns 1.276ns 0.695ns 0.439ns 0.410ns } { 0.000ns 0.590ns 0.442ns 0.292ns 0.607ns } "" } } { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { CLK fenpin:U3|CLK_REG3 TRANSMIT:U1|TXD } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { CLK CLK~out0 fenpin:U3|CLK_REG3 TRANSMIT:U1|TXD } { 0.000ns 0.000ns 0.745ns 4.276ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { CLK fenpin:U3|CLK_REG3 TRANSMIT:U1|TEMP[1] } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { CLK CLK~out0 fenpin:U3|CLK_REG3 TRANSMIT:U1|TEMP[1] } { 0.000ns 0.000ns 0.745ns 4.276ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "BEGINS:U0\|TEMP\[1\] START CLK 1.747 ns register " "Info: tsu for register \"BEGINS:U0\|TEMP\[1\]\" (data pin = \"START\", clock pin = \"CLK\") is 1.747 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.846 ns + Longest pin register " "Info: + Longest pin to register delay is 9.846 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns START 1 PIN PIN_1 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 7; PIN Node = 'START'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { START } "NODE_NAME" } } { "UART.vhd" "" { Text "E:/mywork/UART/UART.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.464 ns) + CELL(0.590 ns) 8.523 ns BEGINS:U0\|TEMP\[0\]~219 2 COMB LC_X15_Y19_N8 4 " "Info: 2: + IC(6.464 ns) + CELL(0.590 ns) = 8.523 ns; Loc. = LC_X15_Y19_N8; Fanout = 4; COMB Node = 'BEGINS:U0\|TEMP\[0\]~219'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.054 ns" { START BEGINS:U0|TEMP[0]~219 } "NODE_NAME" } } { "BEGINS.vhd" "" { Text "E:/mywork/UART/BEGINS.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.867 ns) 9.846 ns BEGINS:U0\|TEMP\[1\] 3 REG LC_X15_Y19_N1 4 " "Info: 3: + IC(0.456 ns) + CELL(0.867 ns) = 9.846 ns; Loc. = LC_X15_Y19_N1; Fanout = 4; REG Node = 'BEGINS:U0\|TEMP\[1\]'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.323 ns" { BEGINS:U0|TEMP[0]~219 BEGINS:U0|TEMP[1] } "NODE_NAME" } } { "BEGINS.vhd" "" { Text "E:/mywork/UART/BEGINS.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.926 ns ( 29.72 % ) " "Info: Total cell delay = 2.926 ns ( 29.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.920 ns ( 70.28 % ) " "Info: Total interconnect delay = 6.920 ns ( 70.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "9.846 ns" { START BEGINS:U0|TEMP[0]~219 BEGINS:U0|TEMP[1] } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "9.846 ns" { START START~out0 BEGINS:U0|TEMP[0]~219 BEGINS:U0|TEMP[1] } { 0.000ns 0.000ns 6.464ns 0.456ns } { 0.000ns 1.469ns 0.590ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "BEGINS.vhd" "" { Text "E:/mywork/UART/BEGINS.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 8.136 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 8.136 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 12; CLK Node = 'CLK'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "UART.vhd" "" { Text "E:/mywork/UART/UART.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fenpin:U3\|CLK_REG3 2 REG LC_X14_Y10_N2 28 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X14_Y10_N2; Fanout = 28; REG Node = 'fenpin:U3\|CLK_REG3'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { CLK fenpin:U3|CLK_REG3 } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/mywork/UART/fenpin.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.276 ns) + CELL(0.711 ns) 8.136 ns BEGINS:U0\|TEMP\[1\] 3 REG LC_X15_Y19_N1 4 " "Info: 3: + IC(4.276 ns) + CELL(0.711 ns) = 8.136 ns; Loc. = LC_X15_Y19_N1; Fanout = 4; REG Node = 'BEGINS:U0\|TEMP\[1\]'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.987 ns" { fenpin:U3|CLK_REG3 BEGINS:U0|TEMP[1] } "NODE_NAME" } } { "BEGINS.vhd" "" { Text "E:/mywork/UART/BEGINS.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.29 % ) " "Info: Total cell delay = 3.115 ns ( 38.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.021 ns ( 61.71 % ) " "Info: Total interconnect delay = 5.021 ns ( 61.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { CLK fenpin:U3|CLK_REG3 BEGINS:U0|TEMP[1] } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { CLK CLK~out0 fenpin:U3|CLK_REG3 BEGINS:U0|TEMP[1] } { 0.000ns 0.000ns 0.745ns 4.276ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "9.846 ns" { START BEGINS:U0|TEMP[0]~219 BEGINS:U0|TEMP[1] } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "9.846 ns" { START START~out0 BEGINS:U0|TEMP[0]~219 BEGINS:U0|TEMP[1] } { 0.000ns 0.000ns 6.464ns 0.456ns } { 0.000ns 1.469ns 0.590ns 0.867ns } "" } } { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { CLK fenpin:U3|CLK_REG3 BEGINS:U0|TEMP[1] } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { CLK CLK~out0 fenpin:U3|CLK_REG3 BEGINS:U0|TEMP[1] } { 0.000ns 0.000ns 0.745ns 4.276ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK XMIT_DONE TRANSMIT:U1\|XMIT_DONE 13.627 ns register " "Info: tco from clock \"CLK\" to destination pin \"XMIT_DONE\" through register \"TRANSMIT:U1\|XMIT_DONE\" is 13.627 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 8.136 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 8.136 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 12; CLK Node = 'CLK'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "UART.vhd" "" { Text "E:/mywork/UART/UART.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fenpin:U3\|CLK_REG3 2 REG LC_X14_Y10_N2 28 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X14_Y10_N2; Fanout = 28; REG Node = 'fenpin:U3\|CLK_REG3'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { CLK fenpin:U3|CLK_REG3 } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/mywork/UART/fenpin.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.276 ns) + CELL(0.711 ns) 8.136 ns TRANSMIT:U1\|XMIT_DONE 3 REG LC_X15_Y18_N9 4 " "Info: 3: + IC(4.276 ns) + CELL(0.711 ns) = 8.136 ns; Loc. = LC_X15_Y18_N9; Fanout = 4; REG Node = 'TRANSMIT:U1\|XMIT_DONE'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.987 ns" { fenpin:U3|CLK_REG3 TRANSMIT:U1|XMIT_DONE } "NODE_NAME" } } { "TRANSMIT.vhd" "" { Text "E:/mywork/UART/TRANSMIT.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.29 % ) " "Info: Total cell delay = 3.115 ns ( 38.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.021 ns ( 61.71 % ) " "Info: Total interconnect delay = 5.021 ns ( 61.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { CLK fenpin:U3|CLK_REG3 TRANSMIT:U1|XMIT_DONE } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { CLK CLK~out0 fenpin:U3|CLK_REG3 TRANSMIT:U1|XMIT_DONE } { 0.000ns 0.000ns 0.745ns 4.276ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "TRANSMIT.vhd" "" { Text "E:/mywork/UART/TRANSMIT.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.267 ns + Longest register pin " "Info: + Longest register to pin delay is 5.267 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TRANSMIT:U1\|XMIT_DONE 1 REG LC_X15_Y18_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y18_N9; Fanout = 4; REG Node = 'TRANSMIT:U1\|XMIT_DONE'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { TRANSMIT:U1|XMIT_DONE } "NODE_NAME" } } { "TRANSMIT.vhd" "" { Text "E:/mywork/UART/TRANSMIT.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.159 ns) + CELL(2.108 ns) 5.267 ns XMIT_DONE 2 PIN PIN_183 0 " "Info: 2: + IC(3.159 ns) + CELL(2.108 ns) = 5.267 ns; Loc. = PIN_183; Fanout = 0; PIN Node = 'XMIT_DONE'" {  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.267 ns" { TRANSMIT:U1|XMIT_DONE XMIT_DONE } "NODE_NAME" } } { "UART.vhd" "" { Text "E:/mywork/UART/UART.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 40.02 % ) " "Info: Total cell delay = 2.108 ns ( 40.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.159 ns ( 59.98 % ) " "Info: Total interconnect delay = 3.159 ns ( 59.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.267 ns" { TRANSMIT:U1|XMIT_DONE XMIT_DONE } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "5.267 ns" { TRANSMIT:U1|XMIT_DONE XMIT_DONE } { 0.000ns 3.159ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.136 ns" { CLK fenpin:U3|CLK_REG3 TRANSMIT:U1|XMIT_DONE } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.136 ns" { CLK CLK~out0 fenpin:U3|CLK_REG3 TRANSMIT:U1|XMIT_DONE } { 0.000ns 0.000ns 0.745ns 4.276ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.267 ns" { TRANSMIT:U1|XMIT_DONE XMIT_DONE } "NODE_NAME" } } { "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus7.0/quartus/bin/Technology_Viewer.qrui" "5.267 ns" { TRANSMIT:U1|XMIT_DONE XMIT_DONE } { 0.000ns 3.159ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}