uart.sim.rpt

自己用VHDL写的一个串口程序

; |UART|TRANSMIT:U1|LEN[1]               ; |UART|TRANSMIT:U1|LEN[1]~212COUT1      ; cout1            ;
; |UART|TRANSMIT:U1|LEN[2]               ; |UART|TRANSMIT:U1|LEN[2]~213           ; cout0            ;
; |UART|TRANSMIT:U1|LEN[2]               ; |UART|TRANSMIT:U1|LEN[2]~213COUT1      ; cout1            ;
; |UART|TRANSMIT:U1|LEN[0]               ; |UART|TRANSMIT:U1|LEN[0]~214           ; cout0            ;
; |UART|TRANSMIT:U1|LEN[0]               ; |UART|TRANSMIT:U1|LEN[0]~214COUT1      ; cout1            ;
; |UART|BEGINS:U0|TEMP[1]                ; |UART|BEGINS:U0|TEMP[1]~146            ; cout0            ;
; |UART|BEGINS:U0|TEMP[1]                ; |UART|BEGINS:U0|TEMP[1]~146COUT1       ; cout1            ;
; |UART|BEGINS:U0|TEMP[2]                ; |UART|BEGINS:U0|TEMP[2]~147            ; cout0            ;
; |UART|BEGINS:U0|TEMP[2]                ; |UART|BEGINS:U0|TEMP[2]~147COUT1       ; cout1            ;
; |UART|BEGINS:U0|TEMP[0]                ; |UART|BEGINS:U0|TEMP[0]~149            ; cout0            ;
; |UART|BEGINS:U0|TEMP[0]                ; |UART|BEGINS:U0|TEMP[0]~149COUT1       ; cout1            ;
; |UART|TRANSMIT:U1|TXD                  ; |UART|TRANSMIT:U1|TXD                  ; regout           ;
; |UART|fenpin:U3|CLK_REG3               ; |UART|fenpin:U3|CLK_REG3               ; regout           ;
; |UART|TRANSMIT:U1|PRESENT_STATE.x_idle ; |UART|TRANSMIT:U1|PRESENT_STATE.x_idle ; regout           ;
; |UART|TRANSMIT:U1|TEMP[0]              ; |UART|TRANSMIT:U1|TEMP[0]              ; regout           ;
; |UART|TRANSMIT:U1|Equal0~46            ; |UART|TRANSMIT:U1|Equal0~46            ; combout          ;
; |UART|TRANSMIT:U1|Selector21~29        ; |UART|TRANSMIT:U1|Selector21~29        ; combout          ;
; |UART|BEGINS:U0|VOUT                   ; |UART|BEGINS:U0|VOUT                   ; regout           ;
; |UART|TRANSMIT:U1|Selector22~490       ; |UART|TRANSMIT:U1|Selector22~490       ; combout          ;
; |UART|TRANSMIT:U1|PRESENT_STATE.x_8    ; |UART|TRANSMIT:U1|PRESENT_STATE.x_8    ; regout           ;
; |UART|TRANSMIT:U1|PRESENT_STATE.x_7    ; |UART|TRANSMIT:U1|PRESENT_STATE.x_7    ; regout           ;
; |UART|TRANSMIT:U1|PRESENT_STATE.x_6    ; |UART|TRANSMIT:U1|PRESENT_STATE.x_6    ; regout           ;
; |UART|TRANSMIT:U1|PRESENT_STATE.x_9    ; |UART|TRANSMIT:U1|Selector22~491       ; combout          ;
; |UART|TRANSMIT:U1|PRESENT_STATE.x_9    ; |UART|TRANSMIT:U1|PRESENT_STATE.x_9    ; regout           ;
; |UART|TRANSMIT:U1|PRESENT_STATE.x_4    ; |UART|TRANSMIT:U1|PRESENT_STATE.x_4    ; regout           ;
; |UART|TRANSMIT:U1|PRESENT_STATE.x_3    ; |UART|TRANSMIT:U1|PRESENT_STATE.x_3    ; regout           ;
; |UART|TRANSMIT:U1|PRESENT_STATE.x_2    ; |UART|TRANSMIT:U1|PRESENT_STATE.x_2    ; regout           ;
; |UART|TRANSMIT:U1|PRESENT_STATE.x_5    ; |UART|TRANSMIT:U1|Selector22~492       ; combout          ;
; |UART|TRANSMIT:U1|PRESENT_STATE.x_5    ; |UART|TRANSMIT:U1|PRESENT_STATE.x_5    ; regout           ;
; |UART|TRANSMIT:U1|PRESENT_STATE.x_1    ; |UART|TRANSMIT:U1|Selector22~493       ; combout          ;
; |UART|TRANSMIT:U1|PRESENT_STATE.x_1    ; |UART|TRANSMIT:U1|PRESENT_STATE.x_1    ; regout           ;
; |UART|TRANSMIT:U1|Selector22~494       ; |UART|TRANSMIT:U1|Selector22~494       ; combout          ;
; |UART|TRANSMIT:U1|PRESENT_STATE.x_wait ; |UART|TRANSMIT:U1|PRESENT_STATE.x_wait ; regout           ;
; |UART|TRANSMIT:U1|Selector22~495       ; |UART|TRANSMIT:U1|Selector22~495       ; combout          ;
; |UART|TRANSMIT:U1|Equal1~40            ; |UART|TRANSMIT:U1|Equal1~40            ; combout          ;
; |UART|TRANSMIT:U1|Selector22~496       ; |UART|TRANSMIT:U1|Selector22~496       ; combout          ;
; |UART|fenpin:U3|COUNTER3               ; |UART|fenpin:U3|COUNTER3               ; regout           ;
; |UART|TRANSMIT:U1|Selector0~26         ; |UART|TRANSMIT:U1|Selector0~26         ; combout          ;
; |UART|TRANSMIT:U1|Add0~103             ; |UART|TRANSMIT:U1|Add0~103             ; combout          ;
; |UART|TRANSMIT:U1|Add0~104             ; |UART|TRANSMIT:U1|Add0~104             ; combout          ;
; |UART|BEGINS:U0|Equal0~41              ; |UART|BEGINS:U0|Equal0~41              ; combout          ;
; |UART|BEGINS:U0|VOUT~30                ; |UART|BEGINS:U0|VOUT~30                ; combout          ;
; |UART|TRANSMIT:U1|LEN[0]~216           ; |UART|TRANSMIT:U1|LEN[0]~216           ; combout          ;
; |UART|TRANSMIT:U1|process0~1           ; |UART|TRANSMIT:U1|process0~1           ; combout          ;
; |UART|BEGINS:U0|PRESENT_STATE.state3   ; |UART|BEGINS:U0|PRESENT_STATE.state3   ; regout           ;
; |UART|BEGINS:U0|PRESENT_STATE.state2   ; |UART|BEGINS:U0|Selector1~65           ; combout          ;
; |UART|BEGINS:U0|PRESENT_STATE.state2   ; |UART|BEGINS:U0|PRESENT_STATE.state2   ; regout           ;
; |UART|XMIT_DONE                        ; |UART|XMIT_DONE                        ; padio            ;
; |UART|TXD                              ; |UART|TXD                              ; padio            ;
; |UART|CLKCESHI                         ; |UART|CLKCESHI                         ; padio            ;
; |UART|CLK                              ; |UART|CLK                              ; combout          ;
+----------------------------------------+----------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------+
; Missing 1-Value Coverage                        ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                       ;
+--------------------------------------+--------------------------------------+------------------+
; Node Name                            ; Output Port Name                     ; Output Port Type ;
+--------------------------------------+--------------------------------------+------------------+
; |UART|BEGINS:U0|PRESENT_STATE.state1 ; |UART|BEGINS:U0|PRESENT_STATE.state1 ; regout           ;
+--------------------------------------+--------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Mon May 14 09:06:41 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off UART -c UART
Info: Using vector source file "E:/mywork/UART/UART.vwf"
Warning: Can't display state machine states -- register holding state machine bit "|UART|TRANSMIT:U1|PRESENT_STATE.x" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|UART|TRANSMIT:U1|PRESENT_STATE.x_stop" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|UART|TRANSMIT:U1|PRESENT_STATE.x_shift" was synthesized away
Warning: Ignored node in vector source file. Can't find corresponding node name "DATAIN[7]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "DATAIN[6]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "DATAIN[5]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "DATAIN[4]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "DATAIN[3]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "DATAIN[2]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "DATAIN[1]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "DATAIN[0]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "RESET" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "START" in design.
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      98.11 %
Info: Number of transitions in simulation is 9770
Info: Quartus II Simulator was successful. 0 errors, 13 warnings
    Info: Allocated 90 megabytes of memory during processing
    Info: Processing ended: Mon May 14 09:06:43 2007
    Info: Elapsed time: 00:00:02