uart.fit.smsg

自己用VHDL写的一个串口程序

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Mon May 14 10:52:27 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off UART -c UART
Info: Selected device EP1C6Q240C8 for design "UART"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 74 of 74 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C12Q240C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 24
    Info: Pin ~ASDO~ is reserved at location 37
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "CLK" to use Global clock in PIN 28
Info: Automatically promoted some destinations of signal "fenpin:U3|CLK_REG3" to use Global clock
    Info: Destination "fenpin:U3|CLK_REG3" may be non-global or may not use global clock
    Info: Destination "CLKCESHI" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 4.400 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y12; Fanout = 4; REG Node = 'fenpin:U3|COUNTER3[7]'
    Info: 2: + IC(1.350 ns) + CELL(0.114 ns) = 1.464 ns; Loc. = LAB_X14_Y13; Fanout = 1; COMB Node = 'fenpin:U3|Equal4~99'
    Info: 3: + IC(0.798 ns) + CELL(0.590 ns) = 2.852 ns; Loc. = LAB_X14_Y12; Fanout = 4; COMB Node = 'fenpin:U3|Equal4~100'
    Info: 4: + IC(1.239 ns) + CELL(0.309 ns) = 4.400 ns; Loc. = LAB_X14_Y10; Fanout = 28; REG Node = 'fenpin:U3|CLK_REG3'
    Info: Total cell delay = 1.013 ns ( 23.02 % )
    Info: Total interconnect delay = 3.387 ns ( 76.98 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X12_Y11 to location X23_Y21
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Allocated 169 megabytes of memory during processing
    Info: Processing ended: Mon May 14 10:52:34 2007
    Info: Elapsed time: 00:00:07