fd.tan.qmsg

这是一个键盘防抖动的C程序。该防抖动程序采用计数器型

{ "Info" "ITDB_TH_RESULT" "lpm_counter:jsq_rtl_0\|dffs\[0\] key clk 13.000 ns register " "Info: th for register \"lpm_counter:jsq_rtl_0\|dffs\[0\]\" (data pin = \"key\", clock pin = \"clk\") is 13.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 19.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 19.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_6 25 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_6; Fanout = 25; CLK Node = 'clk'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "" { clk } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns q\[14\] 2 REG LC3 27 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC3; Fanout = 27; REG Node = 'q\[14\]'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "9.000 ns" { clk q[14] } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 19.000 ns lpm_counter:jsq_rtl_0\|dffs\[0\] 3 REG LC32 11 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 19.000 ns; Loc. = LC32; Fanout = 11; REG Node = 'lpm_counter:jsq_rtl_0\|dffs\[0\]'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "8.000 ns" { q[14] lpm_counter:jsq_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.000 ns 78.95 % " "Info: Total cell delay = 15.000 ns ( 78.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 21.05 % " "Info: Total interconnect delay = 4.000 ns ( 21.05 % )" {  } {  } 0}  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "19.000 ns" { clk q[14] lpm_counter:jsq_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "19.000 ns" { clk clk~out q[14] lpm_counter:jsq_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns key 1 PIN PIN_4 16 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_4; Fanout = 16; PIN Node = 'key'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "" { key } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns lpm_counter:jsq_rtl_0\|dffs\[0\] 2 REG LC32 11 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC32; Fanout = 11; REG Node = 'lpm_counter:jsq_rtl_0\|dffs\[0\]'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "8.000 ns" { key lpm_counter:jsq_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "10.000 ns" { key lpm_counter:jsq_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { key key~out lpm_counter:jsq_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "19.000 ns" { clk q[14] lpm_counter:jsq_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "19.000 ns" { clk clk~out q[14] lpm_counter:jsq_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 6.000ns } } } { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "10.000 ns" { key lpm_counter:jsq_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { key key~out lpm_counter:jsq_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 06 09:34:44 2007 " "Info: Processing ended: Sun May 06 09:34:44 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}