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📄 fd.tan.qmsg

📁 这是一个键盘防抖动的C程序。该防抖动程序采用计数器型
💻 QMSG
📖 第 1 页 / 共 3 页
字号:
🔍
123 
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "q\[14\] " "Info: Detected ripple clock \"q\[14\]\" as buffer" {  } { { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 12 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q\[14\]" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register q\[0\] register q\[16\] 47.62 MHz 21.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 47.62 MHz between source register \"q\[0\]\" and destination register \"q\[16\]\" (period= 21.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.000 ns + Longest register register " "Info: + Longest register to register delay is 16.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[0\] 1 REG LC1 35 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 35; REG Node = 'q\[0\]'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "" { q[0] } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 10.000 ns reduce_nor~4sexp 2 COMB SEXP1 8 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP1; Fanout = 8; COMB Node = 'reduce_nor~4sexp'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "10.000 ns" { q[0] reduce_nor~4sexp } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.000 ns) 16.000 ns q\[16\] 3 REG LC8 19 " "Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 16.000 ns; Loc. = LC8; Fanout = 19; REG Node = 'q\[16\]'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "6.000 ns" { reduce_nor~4sexp q[16] } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns 87.50 % " "Info: Total cell delay = 14.000 ns ( 87.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 12.50 % " "Info: Total interconnect delay = 2.000 ns ( 12.50 % )" {  } {  } 0}  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "16.000 ns" { q[0] reduce_nor~4sexp q[16] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "16.000 ns" { q[0] reduce_nor~4sexp q[16] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 8.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_6 25 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_6; Fanout = 25; CLK Node = 'clk'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "" { clk } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns q\[16\] 2 REG LC8 19 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC8; Fanout = 19; REG Node = 'q\[16\]'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "8.000 ns" { clk q[16] } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "10.000 ns" { clk q[16] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { clk clk~out q[16] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_6 25 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_6; Fanout = 25; CLK Node = 'clk'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "" { clk } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns q\[0\] 2 REG LC1 35 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC1; Fanout = 35; REG Node = 'q\[0\]'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "8.000 ns" { clk q[0] } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "10.000 ns" { clk q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { clk clk~out q[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "10.000 ns" { clk q[16] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { clk clk~out q[16] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "10.000 ns" { clk q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { clk clk~out q[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 12 -1 0 } }  } 0}  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "16.000 ns" { q[0] reduce_nor~4sexp q[16] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "16.000 ns" { q[0] reduce_nor~4sexp q[16] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 8.000ns 6.000ns } } } { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "10.000 ns" { clk q[16] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { clk clk~out q[16] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "10.000 ns" { clk q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { clk clk~out q[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:jsq_rtl_0\|dffs\[2\] key clk -4.000 ns register " "Info: tsu for register \"lpm_counter:jsq_rtl_0\|dffs\[2\]\" (data pin = \"key\", clock pin = \"clk\") is -4.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.000 ns + Longest pin register " "Info: + Longest pin to register delay is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns key 1 PIN PIN_4 16 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_4; Fanout = 16; PIN Node = 'key'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "" { key } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns lpm_counter:jsq_rtl_0\|dffs\[2\]~195 2 COMB LC17 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC17; Fanout = 1; COMB Node = 'lpm_counter:jsq_rtl_0\|dffs\[2\]~195'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "8.000 ns" { key lpm_counter:jsq_rtl_0|dffs[2]~195 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 11.000 ns lpm_counter:jsq_rtl_0\|dffs\[2\] 3 REG LC18 11 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 11.000 ns; Loc. = LC18; Fanout = 11; REG Node = 'lpm_counter:jsq_rtl_0\|dffs\[2\]'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "1.000 ns" { lpm_counter:jsq_rtl_0|dffs[2]~195 lpm_counter:jsq_rtl_0|dffs[2] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 81.82 % " "Info: Total cell delay = 9.000 ns ( 81.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 18.18 % " "Info: Total interconnect delay = 2.000 ns ( 18.18 % )" {  } {  } 0}  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "11.000 ns" { key lpm_counter:jsq_rtl_0|dffs[2]~195 lpm_counter:jsq_rtl_0|dffs[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { key key~out lpm_counter:jsq_rtl_0|dffs[2]~195 lpm_counter:jsq_rtl_0|dffs[2] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 6.000ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 19.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 19.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_6 25 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_6; Fanout = 25; CLK Node = 'clk'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "" { clk } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns q\[14\] 2 REG LC3 27 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC3; Fanout = 27; REG Node = 'q\[14\]'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "9.000 ns" { clk q[14] } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 19.000 ns lpm_counter:jsq_rtl_0\|dffs\[2\] 3 REG LC18 11 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 19.000 ns; Loc. = LC18; Fanout = 11; REG Node = 'lpm_counter:jsq_rtl_0\|dffs\[2\]'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "8.000 ns" { q[14] lpm_counter:jsq_rtl_0|dffs[2] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.000 ns 78.95 % " "Info: Total cell delay = 15.000 ns ( 78.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 21.05 % " "Info: Total interconnect delay = 4.000 ns ( 21.05 % )" {  } {  } 0}  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "19.000 ns" { clk q[14] lpm_counter:jsq_rtl_0|dffs[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "19.000 ns" { clk clk~out q[14] lpm_counter:jsq_rtl_0|dffs[2] } { 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 6.000ns } } }  } 0}  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "11.000 ns" { key lpm_counter:jsq_rtl_0|dffs[2]~195 lpm_counter:jsq_rtl_0|dffs[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { key key~out lpm_counter:jsq_rtl_0|dffs[2]~195 lpm_counter:jsq_rtl_0|dffs[2] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 6.000ns 1.000ns } } } { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "19.000 ns" { clk q[14] lpm_counter:jsq_rtl_0|dffs[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "19.000 ns" { clk clk~out q[14] lpm_counter:jsq_rtl_0|dffs[2] } { 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 6.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk keyout lpm_counter:jsq_rtl_0\|dffs\[0\] 33.000 ns register " "Info: tco from clock \"clk\" to destination pin \"keyout\" through register \"lpm_counter:jsq_rtl_0\|dffs\[0\]\" is 33.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 19.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 19.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_6 25 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_6; Fanout = 25; CLK Node = 'clk'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "" { clk } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns q\[14\] 2 REG LC3 27 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC3; Fanout = 27; REG Node = 'q\[14\]'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "9.000 ns" { clk q[14] } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 19.000 ns lpm_counter:jsq_rtl_0\|dffs\[0\] 3 REG LC32 11 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 19.000 ns; Loc. = LC32; Fanout = 11; REG Node = 'lpm_counter:jsq_rtl_0\|dffs\[0\]'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "8.000 ns" { q[14] lpm_counter:jsq_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.000 ns 78.95 % " "Info: Total cell delay = 15.000 ns ( 78.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 21.05 % " "Info: Total interconnect delay = 4.000 ns ( 21.05 % )" {  } {  } 0}  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "19.000 ns" { clk q[14] lpm_counter:jsq_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "19.000 ns" { clk clk~out q[14] lpm_counter:jsq_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:jsq_rtl_0\|dffs\[0\] 1 REG LC32 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC32; Fanout = 11; REG Node = 'lpm_counter:jsq_rtl_0\|dffs\[0\]'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "" { lpm_counter:jsq_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns reduce_nor~6 2 COMB LC19 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC19; Fanout = 1; COMB Node = 'reduce_nor~6'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "9.000 ns" { lpm_counter:jsq_rtl_0|dffs[0] reduce_nor~6 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns keyout 3 PIN PIN_21 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'keyout'" {  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "4.000 ns" { reduce_nor~6 keyout } "NODE_NAME" } "" } } { "fd.vhd" "" { Text "D:/altera/quartus50/liuhaihai/electronic_lock/fd/fd.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0}  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "13.000 ns" { lpm_counter:jsq_rtl_0|dffs[0] reduce_nor~6 keyout } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { lpm_counter:jsq_rtl_0|dffs[0] reduce_nor~6 keyout } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0}  } { { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "19.000 ns" { clk q[14] lpm_counter:jsq_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "19.000 ns" { clk clk~out q[14] lpm_counter:jsq_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 6.000ns } } } { "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" "" { Report "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd_cmp.qrpt" Compiler "fd" "UNKNOWN" "V1" "D:/altera/quartus50/liuhaihai/electronic_lock/fd/db/fd.quartus_db" { Floorplan "D:/altera/quartus50/liuhaihai/electronic_lock/fd/" "" "13.000 ns" { lpm_counter:jsq_rtl_0|dffs[0] reduce_nor~6 keyout } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { lpm_counter:jsq_rtl_0|dffs[0] reduce_nor~6 keyout } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0}
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